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ATmega6450V

Availability: In production

Deviceimage

Summary

The ATmega6450 is the 100-pin version of the ATmega645 and is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega6450 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. NB! 1.8V version!!

Overview features

Flash EEPROM SRAM Speed Volts
64kB 2048B 4096B 0 - 8MHz 1.8 - 5.5V

Files

Packages

General package info

  100-lead TQFP
Package Lead Code 100
Carrier Type TRAY
Max Package Height 1.2
Body Thickness 1
Body Width 14
Body Length 14
JEDEC MSL 3
Units per Carrier 90
Carriers per Bag 10
Units per Bag 900
Quantity per Reel 1500
Tape Pitch 20
Tape Width 24
Downloadable Files pdf Package Drawing
pdf Tube Tray Drawing
pdf Carrier Tape Drawing
pdf Reel Drawing
Other features Tools
Memory
Flash Memory 64 kB
EEPROM Data Memory 2048 B
SRAM Data Memory 4096 B
General Purpose Registers (Accumulators) 32
MCU Specific
Clock Frequency 0 - 8 MHz
Supply Voltage 1.8 - 5.5 V
Sleep Modes 5
Software Programmable Clock Divider Yes
Hardware Multiplier Yes
I/O Pins 68
On Chip Oscillator Yes
Interrupts 32
Interrupts, External pins 17
Interrupt or Wake-up on Pin Change Yes
Brown-out Detection Yes
Power-on Reset Yes
Fully Static Operation Yes
On-Chip Debug support via JTAG port Yes
IEEE 1149.1 (JTAG) Boundary Scan Yes
Timers / Counters
Timer/Counters (8-bit) 2
Watchdog Timer with On-chip Oscillator 1
Real Time Counter 1
Timer/Counters (16-bit) 1
Pulse Width Modulator 4 ch
Analog I/O
Analog Comparator 1
Analog-to-Digital Converter (10-bit) 8 ch
Programming Modes
In-System Programming via SPI Port Yes
High Voltage Parallel Programming (12V) Yes
Self-Programming via on-chip Boot Program Yes
In-System Programming via JTAG port Yes
Serial I/O
Full Duplex Serial Peripheral Interface (SPI) Yes
2-wire Serial Interface (I2C compatible) Yes
Full Duplex USART 1
Universal Serial Interface Yes
Fuses
EEPROM preserved through chip erase Yes
Reset disabled for IO usage Yes
Divide external clock by 8 Yes
SPM enable Yes
System Clock Prescaler Yes