xplained xmega-a1 board and avrisp mk2

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Ok, I got my xmega xplained board at long last and found there is not 6 pin header for programming, only a 10 pin jtag which supports pdi.

Can I assume that I need to make an adaptor to convert the 6 pin isp header to the 10 with the following pin connections:

10 way jtag ---> 6 way arvisp
pin 2 gnd ---> pin 6
pin 4 vcc ---> pin 2
pin 6 clk ---> pin 5 (rst)
pin 8 data ---> pin 1 (miso)

There is a ledgend on the xplained pcb for the jtag header that appears to show data on pin 3 instead of pin 8. Confused!

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IIRC that is correct (it's been a while since I made up a cable for it) - you should end up with the PDI pins all on one side of the JTAG connector (so not pin 3) in the middle, with the outer two unconnected.

- Dean :twisted:

Make Atmel Studio better with my free extensions. Open source and feedback welcome!

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The Xplained manual is wrong, Pin 3 is the data pin. The schematic supplied in AVR1924.zip shows this. When I connect my programmer "USB Tiny MKII" using Pin 8 I get nothing, but using Pin 3 I get a bit further - but still cannot program the chip.

(I'm concerned that the Vtarget is reported as 5.0v, as I have disabled the USB Power option and feed back the 3.3v Vcc to the programmer.

With Pin 3 connected I get the following avrdude output Any Ideas...:

Quote:

avrdude -v -n -px128a1 -cavrisp2 -Pusb -U flash:w:xmega-a1_xplained-demo.hex:a

avrdude: Version 5.10, compiled on Mar 23 2010 at 15:05:31
Copyright (c) 2000-2005 Brian Dean, http://www.bdmicro.com/
Copyright (c) 2007-2009 Joerg Wunsch

System wide configuration file is "/etc/avrdude.conf"
User configuration file is "/home/euan/.avrduderc"
User configuration file does not exist or is not a regular file, skipping

Using Port : usb
Using Programmer : avrisp2
avrdude: usbdev_open(): Found LUFA AVRISP MkII Clone, serno: 0000A00128255
AVR Part : ATXMEGA128A1
Chip Erase delay : 0 us
PAGEL : P00
BS2 : P00
RESET disposition : dedicated
RETRY pulse : SCK
serial program mode : yes
parallel program mode : yes
Timeout : 0
StabDelay : 0
CmdexeDelay : 0
SyncLoops : 0
ByteDelay : 0
PollIndex : 0
PollValue : 0x00
Memory Detail :

Block Poll Page Polled
Memory Type Mode Delay Size Indx Paged Size Size #Pages MinW MaxW ReadBack
----------- ---- ----- ----- ---- ------ ------ ---- ------ ----- ----- ---------
eeprom 0 0 0 0 no 2048 32 0 0 0 0x00 0x00
application 0 0 0 0 no 131072 256 0 0 0 0x00 0x00
apptable 0 0 0 0 no 8192 256 0 0 0 0x00 0x00
boot 0 0 0 0 no 8192 256 0 0 0 0x00 0x00
flash 0 0 0 0 no 139264 256 0 0 0 0x00 0x00
prodsig 0 0 0 0 no 512 256 0 0 0 0x00 0x00
usersig 0 0 0 0 no 512 256 0 0 0 0x00 0x00
signature 0 0 0 0 no 3 0 0 0 0 0x00 0x00
fuse0 0 0 0 0 no 1 0 0 0 0 0x00 0x00
fuse1 0 0 0 0 no 1 0 0 0 0 0x00 0x00
fuse2 0 0 0 0 no 1 0 0 0 0 0x00 0x00
fuse4 0 0 0 0 no 1 0 0 0 0 0x00 0x00
fuse5 0 0 0 0 no 1 0 0 0 0 0x00 0x00
lock 0 0 0 0 no 1 0 0 0 0 0x00 0x00

Programmer Type : STK500V2
Description : Atmel AVR ISP mkII
Programmer Model: AVRISP mkII
Hardware Version: 0
Firmware Version Master : 1.13
Vtarget : 5.0 V
SCK period : 8.00 us

avrdude: AVR device initialized and ready to accept instructions

Reading | | 0% 0.00savrdude: stk500v2_command(): error in CMD_XPROG: Timeout
avrdude: stk600_xprog_read_byte(): XPRG_CMD_READ_MEM failed
avr_read(): error reading address 0x0000
read operation not supported for memory "signature"
avrdude: error reading signature data for part "ATXMEGA128A1", rc=-2
avrdude: error reading signature data, rc=-1

avrdude done. Thank you.

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Sorry - this is the diag from the Schematic...

Attachment(s): 

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Quote:

(I'm concerned that the Vtarget is reported as 5.0v, as I have disabled the USB Power option and feed back the 3.3v Vcc to the programmer.

The USBTINY MKII uses the AT90USB162 internally, which lacks an ADC - so the firmware fakes the reported voltage. The VTARGET pin is still used for correct voltage translation, but the firmware can't tell you what that voltage is.

- Dean :twisted:

Make Atmel Studio better with my free extensions. Open source and feedback welcome!

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Thanks for clearing that up Dean. I have subsequently metered the XPLAINED board and can confirm that PDI Data is definitely on Pin 3.

I am getting very frustrated with the XMega series, Atmel have really made things difficult, multiple boot loader options, different programming interfaces, poor Linux support, bad documentation and an errata list as long as your arm. I've burnt two weeks of my time and have yet to write a single byte to the MCU!

Next step is a naked XMEGA64A1 on a breadboard.

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The naked XMEGA64A1 chip works as expected. I have wired it in a basic layout with just Vcc, Gnd and the PDI lines connected (and one flashy LED on PORTA[0]).

I did have to add a capacitor after my 3.3V converter (LM3940) which surprised me as I thought my 5V was pretty clean. I'll try the XPlained circuit again using a clean 3.3v supply rather than trusting the USB power as my next test. At least I have eliminated all my test hardware and cables from the equation.

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Looking at the above diagram - is it valid to connect PDI to the TDO pin. TDO is output only, while PDI is bi-directional. If JTAG is enabled won't this interfere with the PDI interface? From what I can tell, JTAG is enabled through a fuse so I suppose we cannot get PDI working unless we first use JTAG to disable JTAG (!?)

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From the AVR JTAG ICE User Guide: Section 4.10

If the JTAG interface is enabled, the JTAG pins cannot be used for alternative pin functions.
They will remain dedicated JTAG pins until either the JTAG interface is disabled by setting the JTAG disable JTD bit in the MCUCSR from the program code, or by clearing the JTAG Enable fuse with a programmer.

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Quote:

Looking at the above diagram - is it valid to connect PDI to the TDO pin. TDO is output only, while PDI is bi-directional. If JTAG is enabled won't this interfere with the PDI interface? From what I can tell, JTAG is enabled through a fuse so I suppose we cannot get PDI working unless we first use JTAG to disable JTAG (!?)

PDI uses a special power-on handshake with a dedicated pin on the AVR to enter PDI mode, and so will override any other functions, including JTAG.

- Dean :twisted:

Make Atmel Studio better with my free extensions. Open source and feedback welcome!

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From the PDI Programming doc - AVR 1612...

The PDI Physical must be enabled before it can be used. This is done by first forcing the PDI_DATA line high for a period longer than the equivalent external reset minimum pulse width (refer to device data sheet for reset characteristics).

The first PDI_CLK cycle must start no later than 100μS after the RESET functionality of the Reset pin was disabled. If this does not occur in time the RESET functionality of the Reset pin is automatically enabled again and the enabling procedure must start over again.

After this sequence, the PDI is enabled and ready to receive instructions. The enable sequence is shown in Figure 3-2.

This can be initiated at any time - not just on Power Up. So if PDI_DATA is tied to TDO (and Low) would it not effectively prevent the programmer from ever holding the signal High long enough to disable the Reset function and initiate PDI mode ?

Thanks for hanging in there Dean, I think I'm clutching at straws here...

Euan.

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I'll run a logic probe over it this evening to see exactly what is happening - I'm determined to get to the bottom of this.

Euan.

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Yes, you can enable PDI mode at any time - the device is held in reset during the PDI handshake, so the JTAG module is disabled.

I suppose the ultimate proof is in the practicals; I've been able to happily PDI program my XPLAIN-A1 over PDI while the JTAG interface was still enabled in the fuses.

- Dean :twisted:

Make Atmel Studio better with my free extensions. Open source and feedback welcome!

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Does the XPLAIN have TDO tied to PDI_DATA on Pin 3, or is PDI_DATA on Pin 8 like the manual says?

My board is the newer XPLAINED board.

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OK, I give up for now - too much time wasted. The two pictures attached show the logic using a 1ms scale. This doesn't show much bit level detail, but shows the bigger picture. Up close the traffic in the first burst is identical. The 128 represents the XPLAINED board, and the 64 is the naked XMEGA64A1 being programmed. The hex file used is based off the same C code but compiled to the target. The logic shown is the PDI_CLK and PDI_DATA.

Attachment(s): 

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At last I have got AVR Studio 5 to load some code into the Xplained board!

I can only assume ATMEL get a buzz out of making this really difficult....

No ISP socket on the board, incorrect pinouts in datasheets, etc etc.

PDI data is on pin 3 not 8 as per datasheets.

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@richard-x46

Can you confirm that you used PDI to programme the board? I'm not familiar with Studio 5 - does it call out to a programmer executable or is the programming internal ? If it calls out to something I'd be interetested in what the command line was.

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I wired up the PDI to the AVRISK mkII, 4 pins only and Studio 5.0 programmed it ok -ish.
Still a bit hit and miss but works enough to burn code.

Now just musing the GPIO port of the Xplained card that's on J3. Marked GPIO 1 to 8 but in actual fact the last two bits go port R and the lower 6 bits port D, how strange is that!

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All,

One thing folks may not realize- many of the "Example" applications in Studio 5 for the XMega XPlain are for the original XPlain board. That board had a somewhat different schematic. The new board is called the "XPlained", and target projects for that specific board are correct (there are very few).

The primary difference is that the GPIO ports are on Port D (except for the upper two bits as mentioned above) with the new board, while the old board had them on Port F. There are other differences as well- I believe the co-processor was changed from a USB chip to a UC3 chip (don't recall the exact models).

You can make the "older" XPlain based projects work by changing the appropriate pin references when switches are used. I haven't gotten into the meat of the other projects to determine what else may need to be changed.

-Reid-
W0CNN