XMEGAxxE5 SPIC Buffer Modes - Explanation

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I am working with the XMEGA E5 Xplained (XMEGA32E5 chip).  I am having difficulty reliably receiving data on the SPIC port.  I suspect my lack of understanding regarding the functional difference between Buffer Modes 1 and 2 is hindering my progress.  I will appreciate receiving some clarification of the very limited information found in the XMEGA E Manual (quoted below). Or perhaps a link to a document providing further explanation on the buffer function of the SPIC port.  I am working in assembler and am not familiar with C, so code examples in C are not as helpful to me as assembler code examples or psudocode.

 

Application details: I am running the SPIC in Master Mode and reading data from an external UART that is functioning as an SPI Slave.  I am enabling the SPI port during initialization and then periodically using the port to receive UART data.  The UART requires a command byte before it will present data to the Master.  I am sending a single byte to the UART and then following that with multiple dummy Tx bytes in order to drive the SCK line and clock data from the UART.  I am reading the SPIC data register after each dummy byte is sent to the shift register to be clocked out.  This is a polled rather than an interrupt driven scheme. The result is that the first three reads of the SPIC data register are junk.  I believe my problem is related to not understanding actual function of the receive double buffer.

 

Buffer Mode 1:
- 2 buffers in reception, 1 buffer in transmission
- Separated interrupt flags for transmission and reception
- 1 SPI transfer must be completed before the data is copied into the shift register, even after SPI enable (1
st data transmitted = dummy byte)

Buffer Mode 2:
- 2 buffers in reception, 1 buffer in transmission
- Separated interrupt flags for transmission and reception
- Immediate write data into shift register after SPI enable. Then, 1 SPI transfer must be completed before the data is copied into the shift register.

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Post your code.

Greg Muth

Portland, OR, US

Xplained Boards mostly

Atmel Studio 7.0 on Windows 10

 

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I asked about the difference between these two buffer modes before and got no replies. The manual's description is terrible, but I think this but (20.5) gives it away:

 

 Buffered mode 1:
The SPI module is single buffered in the transmit direction and double buffered in the receive direction. A byte writ-
ten to the transmit register will be copied to the shift register when a full character has been received. When
receiving data, a received character must be read from the DATA register before the third character has been
completely shifted in to avoid loosing data.

 Buffered mode 2:
The SPI module is single buffered in the transmit direction and double buffered in the receive direction. A byte writ-
ten to the transmit register will be copied to the shift register when the SPI is enabled. Then, one SPI transfer must
be completed before the data is copied to the shift register.

 

I think mode 1 is for slave applications mostly. Basically you can queue up a character to be sent after you receive an initial byte from the master. That's a fairly common way for slaves to operate, the first byte from the master is a command or address or something and the slave just sends a dummy byte.

 

But why you would bother implementing this when you can just load the TX buffer with a dummy byte in mode 2 and wait for the master to assert EN isn't clear. I suppose maybe it's to simplify interrupt code.