Xmega128A3 crystal problems

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I have recently returned to a bunch of boards I had made around this part but gave up on a while back. One of the many problems I encountered was not being able to get a crystal up and running.

Ive just looked at these boards again, double checked power and decoupling, and tried a whole bunch of xtal/cap combos with no joy. I even tried moving the xtal closer to the xmega but nothing seems to help.

Osc is switched to RC32M with the following code from AVR1003:

      CLKSYS_Enable( OSC_RC32MEN_bm );
		CLKSYS_Prescalers_Config( CLK_PSADIV_1_gc, CLK_PSBCDIV_1_2_gc );
		do {} while ( CLKSYS_IsReady( OSC_RC32MRDY_bm ) == 0 );
		CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_RC32M_gc );

and works fine. When the code for a xtal 2to9Mhz is tried instead:

      CLKSYS_XOSC_Config( OSC_FRQRANGE_2TO9_gc,
		                    false,
		                    OSC_XOSCSEL_EXTCLK_gc );
		CLKSYS_Enable( OSC_XOSCEN_bm );
		do {} while ( CLKSYS_IsReady( OSC_XOSCRDY_bm ) == 0 );
		CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_XOSC_gc );
		CLKSYS_Disable( OSC_RC32MEN_bm );

the MCU locks up. An 8Mhz xtal would be used with 15pF caps in the example above, but I have tried xtals from 3 to 16MHz from different manufacturers and caps from 5p6 to 27p all with no luck.

What I dont follow is that with an LED flashing from an ISR (from a timer set up as per AVR1003 and working fine from RC32) why the part locks. Shouldnt the do/while prevent osc changeover if the xtal isnt working as intended?

Anyway if anyone can shed any light on this or suggest a known to work xtal/cap combo for the 128A3 it would be appreciated. I seem to remember a lot of xtal probs with the 128A1 part mentioned in these forums when they were fresh. I'm not sure what the batch is but I have had them (a whole tray :( ) a little over a year.

Thanks,

Anthony

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This works for xmega32 (codevision generated code)

// External 8000,000kHz oscillator initialization
OSC.XOSCCTRL=OSC_FRQRANGE_2TO9_gc | OSC_XOSCSEL_XTAL_16KCLK_gc;
// Enable the oscillator
OSC.CTRL|=OSC_XOSCEN_bm;

// System clock prescaler A division factor: 1
// System clock prescalers B & C division factors: B:1, C:1
// ClkPer4: 8000,000kHz
// ClkPer2: 8000,000kHz
// ClkPer:  8000,000kHz
// ClkCPU:  8000,000kHz
n=(CLK.PSCTRL & (~(CLK_PSADIV_gm | CLK_PSBCDIV1_bm | CLK_PSBCDIV0_bm))) |
	CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;
CCP=CCP_IOREG_gc;
CLK.PSCTRL=n;

// Wait for the external oscillator to stabilize
while ((OSC.STATUS & OSC_XOSCRDY_bm)==0);

// Select system clock source: External Osc. or Clock
n=(CLK.CTRL & (~CLK_SCLKSEL_gm)) | CLK_SCLKSEL_XOSC_gc;
CCP=CCP_IOREG_gc;
CLK.CTRL=n;

// Disable the unused oscillators: 2MHz, 32MHz, internal 32kHz, PLL
OSC.CTRL&= ~(OSC_RC2MEN_bm | OSC_RC32MEN_bm | OSC_RC32KEN_bm | OSC_PLLEN_bm);

// Peripheral Clock output: Disabled
// Note: the correct Disabled direction for the Peripheral Clock output
// is configured in the ports_init function
PORTCFG.CLKEVOUT=(PORTCFG.CLKEVOUT & (~PORTCFG_CLKOUT_gm)) | PORTCFG_CLKOUT_OFF_gc;
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Thanks very much, that did the trick. Now running from the 8 MHz xtal @ 32MHz with a 4x PLL

Now to tame the ADC.

Thanks,

Anthony

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Quote:

Now to tame the ADC.

Start here:

http://blog.frankvh.com/2010/01/...

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Thanks for the info. I'll have a look.

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anthony_k wrote:
When the code for a xtal 2to9Mhz is tried instead:

      CLKSYS_XOSC_Config( OSC_FRQRANGE_2TO9_gc,
		                    false,
		                    OSC_XOSCSEL_EXTCLK_gc );
		CLKSYS_Enable( OSC_XOSCEN_bm );
		do {} while ( CLKSYS_IsReady( OSC_XOSCRDY_bm ) == 0 );
		CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_XOSC_gc );
		CLKSYS_Disable( OSC_RC32MEN_bm );

the MCU locks up.

I think the solution here is to configure the external oscillator as a crystal and not an external clock driver.

Use OSC_XOSCSEL_XTAL_16KCLK_gc instead of OSC_XOSCSEL_EXTCLK_gc.

:wink: