I've recently started using the XMega devices instead of the Mega chips. On the Mega chips (328P/328PB for example), there is a General Timer/Counter Control Register (GTCCR), which can be used to reset the prescaler counter when clearing the timer (PSRSYNC bit), so that there won't be a random fraction of the time period "missing" from the first cycle count. This makes timing interrupts much more precise after timer resets. I can't seem to find the equivalent of this on the XMega chips (I'm using the A series, ATxmega64A4U as an example). Any ideas?