Timer2 frequency in power save mode

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Hello,

 

I am looking for pointers on a strange behavior I see in a test program of mine.

I have an ATmega328P, on which I use Timer 2 in synchronous, CTC mode to get a regular tick at 250Hz.

 

For testing, my interrupt handler just toggles a pin connected to a LED.

The main loop simply sleeps.

 

Now, when the main loop sleeps in IDLE mode, everything works fine, the LED appears dimmed (because it's actually blinking at 125Hz).

However, just changing sleep mode to PWR_SAVE make the LED blink really, really slowly, perhaps 8Hz.

 

Is this the expected behavior? Does timer2 clock change when going in PWR_SAVE mode? Did I miss something about it in the documentation?

Or should I look for a bug in my code?

Last Edited: Fri. Apr 21, 2017 - 06:59 PM
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spectras wrote:
Did I miss something about it in the documentation?

Perhaps.

 

2. If Timer/Counter2 is running in asynchronous mode.
 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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In the "slow" situation, I wonder what is awakening your CPU.  What other wakeup sources are enabled?  WDT perhaps?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Thanks for your time :)

Well, from the table I would get to understand that, when in power_save mode, timer2 would still be able to wake up the CPU?

The relevant line does not have the (2) on it, right?

Last Edited: Fri. Apr 21, 2017 - 07:22 PM
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spectras wrote:
The relevant line does not have the (2) on it, right?

??? Ummmm---

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

Last Edited: Fri. Apr 21, 2017 - 07:40 PM
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What I don't understand is:

=> If relevant column is "timer oscillator enabled", then it has the (2) in all sleep modes, including Idle. Therefore timer2 should shut down in idle mode as well.

=> If relevant column is "Wakeup source - Timer 2", then it does not have the (2) in power save mode.

 

Either way, both columns have the exact same content for Idle mode and Power-save mode, which leaves me confused as to why they behave differently.

 

In addition, section 10.6 - Power-save Mode, states:

 

If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer
Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable
bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set.

 

 

This matches what I see: my ISR still gets called at a regular interval when using PWR_SAVE mode. Only it gets called about 16 times less often, as if timer2 frequency was scaled down 16 times in PWR_SAVE mode compared to IDLE mode. Thus my initial question.

 

To confirm timer2 is really the one triggering my ISR, I changed timer2 frequency, and ISR call frequency changes accordingly. And if I disable timer2, my MCU goes into infinite sleep as expected.

Other timers are turned off. Watchdog is turned off as well. No pin interrupt is enabled. Still confused.

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OKaaaay!

I think I found the answer! It has nothing to do with timer2 being shutdown or anything.

I believe it comes from the start-up time when coming out from powersave.

I'm checking relevant fuse settings to see if it matches the behavior I see, give me a few minutes…

 

 

Alright, so. My MCU is the one that comes with Arduino Uno. It has default fuse settings, with low fuse reading 0xff.

That decodes like this:

  • Use 8-16MHz external, low-power crystal.
  • Set clock stabilization delay to 16000 clock cycles
  • No clock output and no clock pre-divide.

 

So this means everytime the MCU wakes up from PWR_SAVE mode, it re-enables its oscillators and waits for 16000 clock cycles before proceeding with ISR. That's about 1ms at 16MHz. And on top of that, additional delay for the clock to actually stabilize before the 1ms is counted. If the total delay is longer than my timer2 period, I lose interrupts.

 

That's part of the explanation. However I still see the same issue at very low frequencies, albeit less dramatic. So there could be something else going on. I wonder whether clock cycles during start-up sequence are raw clock cycles or post-prescaler clock cycles.

Last Edited: Mon. Apr 24, 2017 - 11:09 AM