I have tried to find an answer to the following by searching the archives of this forum as well as Analog Devices. I've also searched for an answer by searching the Web, I've read the Analog Devices datasheet and Atmel processor SPI datasheet section multiple times. I have tried much experimentation.
I am generating code to communicate to the Analog Devices AD7175-8 ADC using an Atmel SAM4SA16B, Cortex M4 core. I have submitted some of this issue to Analog Devices Tech Support with no real success. The problem may lie with the Atmel SPI communications, as I've implemented it.
Single Master/Multiple Slave Implementation - variable peripheral select mode.
SPI Mode 3 for the ADC, CS3
SPI Mode 0 for the Maxim MCP23S17 I/O expanders, CS1 and CS2
8-bits per transfer
Have not, yet, implemented the Peripheral DMA Controller.
*Attachment 1 - shows the SPI initialization
I have the AD7175-8 eval board and have extensively experimented with register setting and etc and viewed SPI comms on a logic analyzer to understand how the device is configured. It is very difficult with the instrument I have to view the complete configuration, but I can clearly see the read transaction.
This is a custom developed PCB with the Atmel uC, two SPI I/O expanders and the AD7175-8 in the digital section. I have successfully communicated with the two SPI Maxim I/O expanders using this processor's SPI on my PC board.
The ADC uses a different SPI Mode 3, than the I/O expanders. The basis of my ADC communications code is the Analog Device provided Driver C code called "ad7175_generic". I have modified Communications.h and Communications.c, renamed to adcComms.h and adcComms.c respectively, to use the Atmel Software Foundation library SPI interface.
The AD7175-8 has been configured by writing to the registers, slowing acquisition to 60 samples/sec and disabling all channels. This was performed to reduce the occurrence
of the DOUT/RDY* pulses (on MISO), which seemed to be read as random data if they occurred during a register read. I have also sped up the SPI comms to the ADC to 1 MHz.
The SPI configuration writes seemed to complete successfully, however, I cannot be certain because SPI reads are suspect. The ADC does behave as though its data
acquisition process is stopped or slowed.
To verify SPI comms with the ADC, I have tried to do as suggested on page 20 of the Analog Devices datasheet and perform a read on the AD7175-8 ID Register. Note here that the datasheet is a bit unclear regarding the important ID register contents, specified as "0x3CDx". If this register contents should be used to verify comms, then why such a cryptic value? Is 0x03CD or 0x3CDE? A question I have submitted to Analog Devices Tech Support.
* Attachment 2 - the read routine for the ADC
I proceed by performing a read on the ID register and set a breakpoint after the contents are received to validate the value.
First issue - The software does not always read both bytes of the ID register. The logic analyzer shows both bytes being transported...
* Attachment 3 - screen shot of the received data, failed to read both bytes of ID register.
* Attachment 4 - logic analyzer display of the ID register read sequence.
Second issue - It seems I need to read 3 bytes to get all of the register contents. The register contains only two bytes, but there seems to be a byte
of junk that needs to be read. By the way, the read seems correct on the Logic analyzer capture.
Third issue - The logic analyzer shows the read bytes being transported in an order that is as expected. However, the bytes received in the
data buffer, over SPI are in an unexpected order.
* Attachment 5 - screen shot of both ID register byte being read, however, not correct order and a junk byte.
I have battled this for several days and am now stuck. Why does it not always read all of the register contents?
Does the AD7175-8 transmit out a byte as the command opcode is transmitted in, i.e., act as a shift register when receiving a command opcode byte?
Why the third junk byte when I read the ID register? Why are the bytes from the ID register not in sequence as seen on the logic analyzer?
Thanks, in advance, for answers, hints, suggestions, etc..