Sinking current on a logic-high pin

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Hello. This is my first post. I did the usual search before posting so if I omitted anything, please just politely let me know via a private message and I will fix it.

 

My uC is an ATmega 168pa, from an arduino pro mini clone. I take one of the PWM outputs and use a simple low-pass filter to generate a "smoothed" DC analog signal between 0V and ~5V (my logic level). Call this signal S1.

 

From this signal, I'd like to be able to have other DC analog signals which are based on S1, but that are level-shifted, and which draw from a higher voltage source. Specifically, I'd like to create signal S2 from S1 with the following voltages:

S1 S2
0 Vdd-2
1 Vdd-1
2 Vdd
3 Vdd
4 Vdd
5 Vdd

 

So S2 is just a +10V level-shifted version of S1 and clamped to Vdd. I achieve this by tying S1 to Vdd (+12V) via a 10V zener diode and a resistor. S2 is then the node between zener and resistor.

 

My question is: if a pin is configured as an output, is it able to sink current from a higher voltage level? When I set S1 to around +1V, there is the possibility of current flowing from Vdd across the zener, through the low-pass filter and back into the microcontroller pin.

 

The resistor is quite large (10k) as I do not need much current from S2, so at most I would envisage around a milliamp of current entering the microcontroller. I suppose this would wind up on the uC's ground plane, but I do not know what the transistor configuration is like around the pin nor if it can withstand ingress current at all when configured as an output. Can it?

 

I have a schematic but it's largish and I'd have to make a simplified plot to display it. Would that help? Would you need any other information to know if this is safe?

Last Edited: Sat. Oct 14, 2017 - 04:11 AM
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The first note - will you exceed the device specs? Most likely yes, so it is not a good idea.
Most cmos pins have substrate diodes that limit the voltage applied to the pin a diode drop below and above the power rails. Exceed a certain current and you can induce 'latchup' which will most likely kill the chip or a gross excess will melt the silicon. 1mA is considered a 'safe' limit.
Icarus found that flying too close to the sun was a bad idea, so you should look at changing your circuit so you avoid such nasties.

You might want to tell us the end goal and show us a sketch of what you've proposed.

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I'd like to echo Kartman's advice and add a few details. 

 

Like all CMOS devices, the AVR GPIO driver structure consists of a P-channel MOSFET that pulls up to the Vcc rail level and an N-channel MOSFET that pulls down to the ground rail. Yes, MOSFETs will handle (some) current in both directions. The issue with your proposal is the on-resistance of the P-channel FET. The spec sheet shows a voltage drop when it sources current of about 250mV with Vcc=5V and 10mA of load current (Pin Driver Strength, Figure 30-211 in the version I have). We can expect similar behavior for current flowing the other direction. This is getting awfully close to the maximum allowed pin voltage(Vcc+0.5V as shown in Electrical Characteristics > Absolute Maximum Ratings). Failure to observe this rating COULD result in a "melted" MCU though more likely a "melted" (stuck high) GPIO pin. 

 

I would suggest some other external PWM filter scheme. Zener diodes are really not particularly good level shifters. Also, the scheme you propose may be relatively low current when high, but a lot more current when it is low. Plus, the tolerance on Zener diodes tends to be relatively poor (or, you spend a lot for better tolerance).

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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I take one of the PWM outputs and use a simple low-pass filter..

..

My question is: if a pin is configured as an output, is it able to sink current from a higher voltage level?

    First quoted statement implies a resistor and a capacitor. The second quoted statement asks if the pin is able to whatever.. You should ask if your filter is able to keep its preset voltage if asked to sink any amount of current; the answer is no.

 

    RC filters are meant to feed a high impedance load as for example the input of an OP AMP, a MOSFET or a BJT if the base current is very low. A P channel MOSFET (or a PNP BJT transistor), the Zener and the resistor you mention would do the job. From top down: 12V, resistor, Zener, Drain (or Emitter), Source (or Collector), GND. Gate (or Base) connected directly to the RC filter cap. Note that in this case you need to subtract the Gate-Source voltage from the Zener voltage, which is not very well defined and depends on temperature. Emitter - Base voltage is better defined, the disadvantage using a BJT is that it would change a bit the output voltage from the filter.

 

    I would look for a two PWM arrangement in which one would go through an OP AMP and amplified. The relationship between the two done in firmware.

 

    Cheers

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Try this: 

Get four 100k 1% resistors and a good rail-rail output opamp & run it at Vdd=12V...so it will limit its output to very close to +12V (the rail)

 

Apply one resistor from the output to - signal input pin & one from - signal input pin to gnd.  Apply two resistors to the + signal input pin.  One of these connects to your PWM source  & the other to a +10V source (such as a 1k pot set to 10V).

This will add 10V to your signal until the opamp output can't go any higher (that may or may not be accurate enough for your app).

 

You can add maybe 100pf in parallel with the "output to -" resistor  & one 0.01uF  at the + input pin to gnd, to reduce noise.

 

When in the dark remember-the future looks brighter than ever.

Last Edited: Sun. Oct 15, 2017 - 12:08 AM
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Welcome to the forum.

 

+1 on using an op-amp.

 

As the PWM needs a LPF one could additionally incorporate the LPF and a gain of perhaps 3 in the op-amp stage.

 

Then use software to set the PWM duty cycle so as to set the desired output voltage, which, when filtered and multiplied by the op-amp gain gives you the desired output voltage.

 

Safe, easy, in-spec, etc.

 

JC

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Thank you all for your advice.

 

The op-amp strategy is a bit too costly for me since I have so many of these circuits in my system. This circuit is most similar to an H-bridge driver. It has four outputs for each input, and the system has quite a few degrees of freedom. While I recognize that it's the ideal answer, I think I'd need two for each driver circuit and I don't have space for so many op-amps.

 

To answer @angelu's point about the RC filter, this driver circuit does indeed feed a high-impedance input (a FET gate). While the filter itself will not sink any amount of current, the most it can receive from Vdd is around 250mA, and that's after the Zener drop. So the source of that reverse current would be at most +2.5V.

 

Say I set the duty cycle to 10%. This produces a steady-state S1 of around +0.5V. Once the RC cap is charged, that 250uA is (I think) going straight into the uC's ground plane during the low phase of the PWM cycle. During the high phase, it's going into the RC cap. But that amount of current is dwarfed by what the uC itself is sending (around 4-5mA).

 

It also dawned on me since authoring this post that the RC filter itself will send current back into the uC when the PWM cycle is in its ground state, even if there were no other voltage source and you were just driving a FET gate. Obviously, the amount depends on the R value. But I've seen people use this "PWM DAC" technique all over the web for driving FETs, so based on that (naive) reasoning, I'm going to assume that it's safe as long as you mind the amount of current.

 

Last Edited: Sat. Oct 21, 2017 - 10:37 PM
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It has four outputs for each input

What do you mean?

Also, opamps can be very cheap......if you took that out, you woudln't even have an circuitry...are you looking for a solution that requires no circuit?!!? 

 

the RC filter itself will send current back into the uC when the PWM cycle is in its ground sta

yes that is normal and usually perfectly fine. 

 

as an output, is it able to sink current from a higher voltage level

generally NO, ...if a pin is low going  to a 1K  resistor & the other end is wired to 12V , then YES it is sinking. but if the pin is turned off, it will not be pulled up to 12V...it will clamp to  Vcc (5 or 3v) & continue to sink from that voltage...the clamping is due to internal diodes in the micro, and is generally not recommended.   I've seen some micros that have 1 or 2 special I/O open drain pins that are rated for much higher voltage (say 24v?)...but don't remember who/what chips they were.  How many of these voltage drive signals do you need?  Your requirement have been somewhat poorly stated.

 

 

 

When in the dark remember-the future looks brighter than ever.

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You're drip feeding us information. if you would like more specific advice, then post a sketch of what you want to do. Otherwise, we can discuss pros and cons of a given technique until the cows come home, but unless you can put numbers to it, then we're just guessing.
You can simulate your circuit using Spice and the various other analog simulation programs. This should give insight into whether your circuit will work in practice.

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You have "sourcing" and "sinking a bit wrong. A logic low  pin SINKS if the current if from a positive source, such as Vcc. A logic high pin SOURCES if the  current is to a lower voltage (often ground). 

 

In the case of an RC PWM filter, the pin sinks current from the capacitor (through the series resistor) when the logic output is low. And it sources current INTO the capacitor (through the series resistor) when the logic output is high.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Here is a rather rare example of high voltage open drain pin  (one SPECIAL pin)...hard to find when you decide you want to search for one...maybe other micros have a bunch on one chip, dunno

 

When in the dark remember-the future looks brighter than ever.

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Kartman: You're drip feeding us information.

Yes, I apologize. But maybe I said more than I needed to. Most of these details are irrelevant to the original question, which can be stated tersely as,

 

"Can an ATmega168P output pin configured for PWM mode sink X amount of current from a higher voltage source?"

 

I needed to add that X is at most 250uA. So, there is some other resistance between the higher voltage and the pin that limits the current to that amount.

 

The low PWM phase is trivial and the current winds up going into the uC ground plane. It's the high phase that I'm principally concerned about, where you can have current (though smaller than X) entering the uC. I'm guessing that there is some logic level plane that could theoretically sink a small current like this. But my hypothesis is that if the uC is not also sourcing this much current as output on some other pin or internal circuitry, then it may artificially raise the voltage of Vcc by some small amount or induce damage.

 

Beyond that, I do not need advice on the design of the circuit itself.

Last Edited: Sun. Oct 22, 2017 - 12:13 AM
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By the way, to add to what Jim mentioned...a super handy rule is the average capacitor current in any continuously running circuit will be zero & the average inductor voltage will be zero (for ideal & non-varying components values).

When in the dark remember-the future looks brighter than ever.

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Hello Jim, and thank you for replying again.

 

I definitely understand you and the canonical use of these terms, but I am talking about a case where a logic high pin may actually sink a small amount of current due to the presence of a higher voltage source and a path between that source and the pin. As I've added in another comment in this thread, that path has a resistance high enough to guarantee at most 250uA of "reverse" current onto the pin in either its low or high state (less than 250uA in the high state).

 

I added that an RC filter is also part of this path. If the pin is high and the cap is nearly fully charged, there can still be a current into the uC during its logic high phase due to this other voltage source.

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'Logic level plane' ? Power planes are on your pcb. There's no need to guess - the current will flow through the substrate diode to Vdd. As to what happens with Vdd, that depends on the enternal circuit. Nevertheless, you are injecting current into the substrate. 250uA will probably be safe, but if you've got a number of outputs doing this, it might not be a good idea. Peak currents can also ruin your day.

If you exceed the max ratings of the device and rely on a 'feature' of the chip that is not specc'ed and not guaranteed, then you're into no-mans land. Whilst it 'might work', you may find you get failures in the field and a die change might cause your circuit not to function. So, do ya feel lucky?
I've had situations where reverse flow has jacked up the vdd and activated an external transzorb diode and promptly melted down.

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Kartman wrote:
'Logic level plane' ? Power planes are on your pcb.

 

That's sort of what I mean -- implying that other board-level devices like the voltage regulator or a capacitor are at risk. Sorry, I've been in the hobby for a couple years but only started talking to people about it this month. I'm sure my vocabulary is awkward at best.

 

Kartman wrote:
Whilst it 'might work', you may find you get failures in the field and a die change might cause your circuit not to function. [/quote]

 

Well, I do feel somewhat lucky at this point, but I don't think that my design would be hurt by the addition of an extra diode after the LPF. That way the only currents re-entering the uC are the ones that it produced in charging the cap.

Last Edited: Sun. Oct 22, 2017 - 02:05 AM
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Hermitude wrote:

... I am talking about a case where a logic high pin may actually sink a small amount of current due to the presence of a higher voltage source and a path between that source and the pin. As I've added in another comment in this thread, that path has a resistance high enough to guarantee at most 250uA of "reverse" current onto the pin in either its low or high state (less than 250uA in the high state).

 

Yes, that is fine, in most cases.

The MOSFETS act like a simple resistor, in both source and sink directions, up until the clamp diodes start conduction.

At some 15~30 ohms ohms, 250uA will be 7.5mV above VDD pin.

Even if the pin is tri-stated, the clamp diodes will clamp ~ 600mV above Vdd. 

 

You do need to ensure the total system current can never go below 250uA ( * N?), otherwise the whole Vdd can lift, and that can damage things quickly (or, use a special regulator that can source and sink).