SAME70 SPI MODE 0 one bit shifted

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Hi,

Im trying to interface SAME70 as mater to slave device which supports SPI mode 0 ( inactive CLK = 0V and data captured on leading edge (rising) and changed on following edge (falling).  And Im using NPCS3.  I have successfully setup the SPI device CPOL= 0 and NCPHA = 1 (SPI_CSR[3]=0x1014802). Writing data is fine but reading data is corrupted and Im reading one bit shifted data.  (ie 0xFE intead of 0xFF or 0x60 instead of 0x30. I have tried to use ASF or some another Atmel SW package to setup the SPI and always with the same output.  In attachment is picture from OSC where is visible that the  transfer is OK  - the first two rising edges are 0 and then next two edges are 1 and the rest have to be 0, so it should be 0x30 but SPI returns 0x60. The preceding and following bytes are bad too.

 

Any ideas what should be wrong?

 

Regards,

Jiri

 

 

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According to your scope I guess data changes on rising edge and therefore should be sampled on falling edge. Data should be 01100000 = 0x60 ? Try NCPHA=0 / CPOL = 0. If you expect to read 0x30 instead of 0x60 then the previous write failed, too.

SAME newbie

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Hi, 

Im almost 100%  sure that the writing is OK as I can see the expected answer on SPI lines. The bit change on MISO is slightly after rising edge, nRF52 chip can read this. I have attached newer OSC picture where the change is between rising edge and falling edge and it is more visible.  I have also tested all SPI modes without any success. 

 

Regards,

Jiri

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kubiajir wrote:
The bit change on MISO is slightly after rising edge

Exactly what I said, on Master read the slave changes data output after rising edge and the master should therefore sample data at falling edge.

So do you see the correct value on master read on the scope but the MPU does show up exactly the data but 1 bit shifted ? Did you try NCPHA/CPOL=1 too ? What if you use slower baud rate ? Are there opto couples between master and slave ?

SAME newbie

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Can you show CS signal too ?

SAME newbie

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Hi, 

yes it looks lika that the master is sampling at falling edge and not the rising edge but it should not. The actual configuration is:

CPOL  = 0   The inactive state value of SPCK is logic level zero.

NCPHA = 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.

 

I have tested all 4 variants of  CPOL NCPHA, slower or faster baud rate but without any success. 

(actually 3 people independently take a look at this here without any success, Im expecting that it will be some tricky bit missing in configuration somewhere. I have already contacted support with this, it is not behaving as it written in datasheet )

 

Regards,

Jiri

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Here is picture of

CS (white 1)

MOSI  (white 2)

MISO  (white 3)

CLK (yel)

 

And again the MISO is changed slightly after rising edge.

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Can you provide SPI timing of the slave ? Is the baud rate 2 Mhz ?

SAME newbie

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Hm. Are you sure that both screenshots show the same SPI mode ? In the first screenshot MISO changes slightly before falling CLK / long after rising clock. In the second sceenshot it seems to me it is the other way around ?

What data do you expect to read in the second screenshot ? 0xFF or 0xFE for the first byte ?

SAME newbie

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kubiajir wrote:
The actual configuration is: CPOL = 0 The inactive state value of SPCK is logic level zero. NCPHA = 1 Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.

 

Looking at the timings in the Figure 40-3 and 40-4 in the E70 data sheet:

I guess using the wrong mode might cause that the data is shifted by one bit, because:

If NCPHA=1 the master expects that the slave outputs its MSB with the falling edge of CS.

If NCPHA=0 the master expects that the slave outputs MSB after the first CLK toggle.

Does this make sense ?

SAME newbie

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Hi,

I have only two channel oscilloscope so I used internal memory to create picture with CS,CLK, MOSI and MISO, it is possible that there is few us skew. Im 100% sure that the MISO is changed after rising edge. In all pictures I have posted I have received the same output from SPI. The slave pre-initialization speed is <3MHz and after initialization it must be <18MHz. 

Your are not correct the MISO MSB must be prepared before first CLK toggle. And as it is in table 40-4 SPI Bus Protocol Modes for SPI mode 0 data shift have to be at falling edge (which actually is somewhere between rising and falling edge) and capture have to be at rising edge which does not seems to be.  And when I connect it to the nRF with SPI_mode_0 configuration then I can read the data correctly. 

Regards,

Jiri

 

 

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Regarding figure 40-3 Master reads MSB at 1st rising edge of CLK from MISO. According to the E70 timing requirements the data must be valid ca. 12ns before rising edge in order to be properly read.

If the slave does output its MSB after the 1st rising edge of CLK then this data is read at the 2nd rising edge of CLK. In my understanding this can cause a shift error. Please correct me if I am wrong.

SAME newbie

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Did you connect the scope at the MPU pins or the slave pins ? I have seen boards with logic inverter in SPI signals. This would explain your assumption that data is sampled at falling edge.

SAME newbie

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Regarding the first screenshot I agree that the E70 should read 0xFF here if it is configured with CPOL=0 & NCPHA=1. If it reads 0xFE here then it seems that it is sampling on falling edge and there is a mistake in the E70 spec.

 

What is confusing me:

Regarding the E70 manual the master expects that in SPI mode 0 the slave changes MISO output on falling edge.

You say that the slave is SPI mode 0 compatible and that according to your scope output the slave changes output is somewhat between rising and falling edge of CLK. What means to me that the rising edge triggers the output change. What means to me that this slave is not a mode 0 compatible device. Can you help me to get these things right ?

 

SAME newbie

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Hi,

just quick answer, I will fully respond lately today. The support guy confirm me today that the table 40-4 is incorrect.

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Hi,

would you pls share this important information with us ?

Thanks,

Jochen

SAME newbie

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Hi,

so far no progress. I have been off last two weeks and I will return to this issue soon. How ever I have discussed this issue with the slave device manufacturer personally and we have measured that the device change its MISO cca 30ns after the first edge (rising edge in this case) which is unusual but correct. The guys from Microchip support sends me some code example but I didnt had time to test it. 

I will let you know in next few days.

Regards,

Jiri