## opamp AC square wave to to DC

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Hi All

I got a op amp that is inputted with a square wave, the op amp generate a +-1.65V AC square wave.

I would like to read that in a ADC, how can i convert that to DC signal so that ADC can read it.

Thank You

Thanks

Regards

DJ

You have no negative power rail to the opamp, so it is unipolar. What is the problem in measuring it?

I am using  a volt meter to make sure my circuit is OK before i use a ADC.

The output of the amp is still AC, as its +-1.65V, and its a square wave.

My aim is to have resistance from about 167K to 5M and these will be placed between IN and OUT. These resistance represents EC from 0.2 to about 6EC

The  aim is to have VOUT range from 0 to 3.3V, but it outputting

1.65V when IN OUT has no resistance.

1.60V when 200K

1.24V when 1M

1.44V when 2M

1.52V when 3M

1.55V when 4M

Does not seem right, as i am trying to get a proportional output.  Do i need to make the square wave to a analogue wave?

Thanks

Thanks

Regards

DJ

If you measure between pin 3 and 1, it looks like the signal is ±1.6V; however, if the ADC is connected between GND and 3V3 (pins 4 and 8 of the opamp), then it will see a square wave from 0 to ~3.2V. Sampling the waveform, the ADC should read the low and high voltage levels fine...

(Or are you trying to determine the duty cycle of the waveform by converting the wave to a DC voltage?)

More details on exactly what you wish to accomplish would help us help you.

David (aka frog_jr)

Let me guess, you're wanting to measure conductance and you need to apply an AC signal? If the micro is controlling the AC signal then you know when to sample the adc.

You know the time that the signal changes, so just sample with the ADC at the appropriate time and let the ADC convert. Just a few dozen ADC clock cycles before the GPIO goes from low to high should do it.

The big problem with this scheme is that you only have a dynamic range of Vcc/2 to (about) Vcc.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sun. Jul 30, 2017 - 01:45 AM

?

Are you trying to make an integrator or an attenuator?

JC

Last Edited: Sun. Jul 30, 2017 - 02:48 AM

if the period is longer than (about) 2.8us, the 10pf feedback cap just slows the rise and fall. It does NOT do much averaging. So far, we know nothing about the switching rate.

If the OP tries to use an active rectifier, it will still only have a range of Vcc/2 to about Vcc. Now, if you AC couple it, and clamp the negative half cycle to ground, THEN you might get something close to a range of 0 to Vcc after subsequent peak detection.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sun. Jul 30, 2017 - 03:05 AM

how can i convert that to DC signal

You need to be more specific--do you want: average?, rms?  Peak-to-peak?  what you turn a whole waveform into a single number, there are many possibilities.  You could use a short circuit & easily convert it to the DC level called zero.

Your level shifter is the beginning of a possible correct approach...maybe add an RC filter, or an rms detector...or  take a lot of samples & do the math (avg, rms, pk-pk, etc) in the micro

When in the dark remember-the future looks brighter than ever.

From Msg #3, it is clear that the OP wants to convert resistance between the "in" and "out" terminals into an ADC reading.

First, contrary to the OP's desires, it will NEVER be linear because the test resistance (167K to 5M) is in parallel with 167K. It would be close to linear if there were no fixed 167K but you need that for circuit stability, so the nonlinearity will have to be lived with.  It may work better if that fixed resistor is large, like 5M (practically, 4.7M or maybe even 10M. While this would be MORE linear, that is only relative and it will still NOT be linear.

Second, there is nothing linear that can be done at the output to get a full range of 0V to Vcc. Simple rectification WILL NOT do it. There are no simple RC networks that will do it. My suggestion of AC coupling followed by clamping the negative half of the square wave to ground, then measuring the positive side with the ADC (using the inherent sampling gate at the ADC input) will get the largest possible range without further amplification.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sun. Jul 30, 2017 - 06:43 AM

From Msg #3, it is clear that the OP wants to convert resistance between the "in" and "out" terminals into an ADC reading.

Um, wouldn't a simple opamp current source driving his resistor accomplish it?  Or just make the unknown a gain resistor   Vout=k(1+A/B) let A be the unknown & subtract the offset (k)...no need to convert AC to Dc at all.

Strange writing by the OP does not help help:

These resistance represents EC from 0.2 to about 6EC   ?????

When in the dark remember-the future looks brighter than ever.

The OP has "obviously" designed it so that the unknown resistance has symmetrical excitation (maybe for use as a water conductivity sensor?). For doing symmetrical excitation, the circuit is pretty good BUT (1) it NOT linear and (2) you need to go to significant effort to measure the output.

Here is another scheme that does the equivalent of the ground clamp that I described in Msg #10. Use TWO ADC channels. Set up one to sample in the middle of the positive half cycle. Set up the other to sample in the middle of the negative half cycle. Take the difference. The DIFFERENCE will go from near zero to near full scale. And it takes less hardware and power consumption.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sun. Jul 30, 2017 - 02:30 PM

Kartman wrote:

Let me guess, you're wanting to measure conductance and you need to apply an AC signal? If the micro is controlling the AC signal then you know when to sample the adc.

Yes i need the AC signal for the probes, as i believe it corrodes less.  My AC signal is 43.2 Khz, i think ADC can be sampled to that.

At the moment i am using a volt meter, i thinking i will set up an adc.

Thanks

Thanks

Regards

DJ

ka7ehk wrote:

You know the time that the signal changes, so just sample with the ADC at the appropriate time and let the ADC convert. Just a few dozen ADC clock cycles before the GPIO goes from low to high should do it.

The big problem with this scheme is that you only have a dynamic range of Vcc/2 to (about) Vcc.

Jim

Just going to set up a ADC, instead of using a voltmeter. With a scope you do notice the amplitude decreasing as resistance increases.

Thanks

Regards

DJ

ka7ehk wrote:

From Msg #3, it is clear that the OP wants to convert resistance between the "in" and "out" terminals into an ADC reading.

First, contrary to the OP's desires, it will NEVER be linear because the test resistance (167K to 5M) is in parallel with 167K. It would be close to linear if there were no fixed 167K but you need that for circuit stability, so the nonlinearity will have to be lived with.  It may work better if that fixed resistor is large, like 5M (practically, 4.7M or maybe even 10M. While this would be MORE linear, that is only relative and it will still NOT be linear.

Second, there is nothing linear that can be done at the output to get a full range of 0V to Vcc. Simple rectification WILL NOT do it. There are no simple RC networks that will do it. My suggestion of AC coupling followed by clamping the negative half of the square wave to ground, then measuring the positive side with the ADC (using the inherent sampling gate at the ADC input) will get the largest possible range without further amplification.

Jim

Jim very sorry, the 167K is not static, this resistance changes as it represents EC.  The resistance symbol is simply there for reference only.

Thanks

Regards

DJ

Ah, Ok, so EC represents the capacitance of the water, causing an impedance that depends on frequency and appears in parallel with the actual resistance.

edit: EC = electrode capacitance, I suppose.

Last Edited: Sun. Jul 30, 2017 - 02:49 PM

ka7ehk wrote:

The OP has "obviously" designed it so that the unknown resistance has symmetrical excitation (maybe for use as a water conductivity sensor?). For doing symmetrical excitation, the circuit is pretty good BUT (1) it NOT linear and (2) you need to go to significant effort to measure the output.

Here is another scheme that does the equivalent of the ground clamp that I described in Msg #10. Use TWO ADC channels. Set up one to sample in the middle of the positive half cycle. Set up the other to sample in the middle of the negative half cycle. Take the difference. The DIFFERENCE will go from near zero to near full scale. And it takes less hardware and power consumption.

Jim

Hi Jim

I agree it will not be linear, so eventually i will need to do some calibration against reference EC and not down the V out values. But before i do that i need to be able to read the VOUT accurately.

I am very much interested in what you mentioned about using two ADC channels. So that i have understood it well.

For example:

Does VOUT go to two ADC channels.

So channel 1 sample will give me a value from 1.65V to 3.3V

Channel 2 sample will give me a value from 1.65V to 0V.

If my AC signal for example is 44Khz.

Would my channel 1 sample rate be 11Khz, which i believe will be in middle of my + cycle and 33 Khz will be at middle of my - cycle?

Thanks

Thanks

Regards

DJ

Yes, you are right about the "interleaving" of the two ADC channels. No, you are wrong about sample rate. BOTH sample at the square wave frequency, just with different delays (say, from the rising edge). At 44KHz, the period is 227us. Delay the first 227/4 us from the rising edge and the second 3*227/4 us from the rising edge.

HOWEVER, 44KHz is too high for the ADC. If you cannot slow the frequency down, then sample, lets say, every 4th cycle with one offset by 2 cycles relative to the other (plus the offset for high and low half cycles).

What is to your ADVANTAGE is that the ADC has a sample and hold at its input. It stays closed for 1/2 ADC clock. So, you need to make sure that the high side has an input that remains high for the whole sample gate time. Ditto, the low ADC channel.

What you MAY need to do is run your timer at 4X the signal rate. Every other tick, toggle the output switch in software. Count ticks (in software) to determine when to sample.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sun. Jul 30, 2017 - 04:19 PM

The OP has "obviously" designed it so that the unknown resistance has symmetrical excitation

No, I don't think so.  OK, zero bias, see Stan's comment below!

There is still a DC bias with the above circuit.

This isn't a symmetrical, (about ground), driver.

There is a "virtual ground" for the op-amp, only.

There is no driven ground with a true bi-polar excitation signal across the electrodes.

Capacitively  coupling the drive signal would help.

But we haven't hear what the setup is, and any additional current paths to ground.

Net electrolysis of the electrodes will likely, (I believe), still occur with the above setup.

OP still hasn't answer what he is trying to measure, (resistance, capacitance, etc.), or what, and what, specifically, he thinks his op-amp circuit is going to do.

JC

Edit:Typo

Edit: Mistake!

Last Edited: Sun. Jul 30, 2017 - 08:16 PM

If the system is battery powered, then "0V" is arbitrary. Yes, there is a bias, relative to many things, but not relative to the resistance being sensed.

The OP HAS stated what is to be measured: 167K to 5M. The implication is resistive but the OP may be surprised on this one. I suspect that it is a water conductance meter or polarimetry meter or maybe even a pH meter. Possibly, a gas sensor or humidity sensor.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sun. Jul 30, 2017 - 04:24 PM

It would appear to me that the signal driver is switching between 0 V drive, and Vcc V drive, with the reference of 0 V, (which, granted, is arbitrary IF on batteries).

But that is still not a symmetric drive with electron flow in both directions.

It is a pulsed drive with electron flow in one direction only, when energized.

Hence there is still a net, DC bias, and electrolysis and other electrode / solute interface concerns exist.

I think.

(Or perhaps it is time for either more sleep, or nor caffeine...)

JC

Yes it is resistance and a water conductance meter.

It is also battery powered.

Quote:
At 44KHz, the period is 227us. Delay the first 227/4 us from the rising edge and the second 3*227/4 us from the rising edge.

Ok that is understood.

Unfortunately i am stuck with 44 khz, but will try and see if i can reduce it.

My AVR clock is 11.0592 Mhz, so with  prescaler 64 my ADC sample rate would be 1728 Khz, so why would 44 khz be an issue?

Quote:
HOWEVER, 44KHz is too high for the ADC. If you cannot slow the frequency down, then sample, lets say, every 4th cycle with one offset by 2 cycles relative to the other (plus the offset for high and low half cycles).

Does that mean i have the ADC write to an array and just take the value of the 4th write?

Quote:
What you MAY need to do is run your timer at 4X the signal rate. Every other tick, toggle the output switch in software. Count ticks (in software) to determine when to sample.

I need to make the rising edge of signal and the timer counting happens at the same time.

Why not just run the ADC continuous on the rising edge of Sqaure wave output, but only acknowledge every 4th value?

Thanks

Regards

DJ

Last Edited: Sun. Jul 30, 2017 - 05:36 PM

djoshi wrote:
Unfortunately i am stuck with 44 khz, but will try and see if i can reduce it. My AVR clock is 11.0592 Mhz, so with prescaler 64 my ADC sample rate would be 1728 Khz, so why would 44 khz be an issue?

I think you forgot the decimal point there. Anyway, you are not supposed to run the ADC at > 200 KHz if you want to keep the 10 bit resolution, so let's say you set the divisor to 64 to get 172.8 kHz. The ADC takes 13 clocks for each conversion, so the sample rate is just 13.3 kS/s.

You will need to run at 4x this speed to keep up with the square wave, that is use divisor 16 and run the ADC at 691 kHz (53 kS/s). This is possible, but will likely result in conversion errors.

It is being argued here that there is DC bias in the OP's schematic at the IN/OUT sensing connection, however with R1/R2 setting the bias at the op amp (-) input to 1/2 Vcc, 1.65v, then the op amp summing (+) point will also be at 1/2 Vcc. With a GPIO supplied square wave applied to one side of the sense connection, between Vcc and common, and the other side to R3, which is being held at 1/2 Vcc by the op amp -- to me this appears to be symmetrical with no effective DC bias, as long as there is no other connection to the process being sensed. If the minimum resistance applied to the input was 167K, the GPIO would be supplying about 10µA through the sense connection and R3 to the op amp summing junction, nearly insignificant for a GPIO drive. The LMV341 is specified as a R/R output device where the +/- output swings are nearly the same with a drop of less than 1mV at 10µA.

Stan

El Tangas wrote:

djoshi wrote:

Unfortunately i am stuck with 44 khz, but will try and see if i can reduce it. My AVR clock is 11.0592 Mhz, so with prescaler 64 my ADC sample rate would be 1728 Khz, so why would 44 khz be an issue?

I think you forgot the decimal point there. Anyway, you are not supposed to run the ADC at > 200 KHz if you want to keep the 10 bit resolution, so let's say you set the divisor to 64 to get 172.8 kHz. The ADC takes 13 clocks for each conversion, so the sample rate is just 13.3 kS/s.

You will need to run at 4x this speed to keep up with the square wave, that is use divisor 16 and run the ADC at 691 kHz (53 kS/s). This is possible, but will likely result in conversion errors.

I have now set my output clock to the circuit to about 11 khz and it seems to be working.

So i guess i am now within the limits of the ADC,

Thanks

Regards

DJ

The resistor is a representation  at IN and OUT of EC, 167K is about 6EC.

When used with water this resistor will not be there.

Thanks

Regards

DJ

Hi Stan, nice catch, my error!

Thank you for correcting it.

JC

Dear Jim

When you mentioned that i need add a delay from rising edge of the signal coming into the ADC, do i simply detect a pin change rising edge and then starts the ADC?

How is the sample delayed to our desired location?

Thanks

Thanks

Regards

DJ

I might be wrong , but wouldn't the amplitude proportionality for the positive square be the same as the negative square wave?  So the difference between them will be twice as much as reading the positive.

Maybe i am wrong....

Thanks

Regards

DJ

How is the sample delayed? With a timer or a programmed delay.
As for a the positive a negative values - is the adc unipolar or bipolar? I'm guessing unipolar- so look for the difference.

It is Unipolar.

Programmed delays or timers are fine, but how do i know when to execute a delay?

Do i use the GPIO rising edge interrupt, but if the voltage is low then it would not see it as a high.

Thanks

Regards

DJ

what is generating the ac signal? You really are making this difficult for all of us as you hold back critical information. Look at how many posts were wasted trying to figure out what you were wanting to achieve.

Its a timer generating a pwm output.

Thanks

Regards

DJ

Are you using pwm? Why not ctc mode with toggle?
You can enable an interrupt on compare.

Yes i am in pwm mode. This was to done to insure i get a good square wave as i can easily set the duty cycle. But i guess i could do the same with ctc and some software.

So on a ctc interupt i enable adc to take one sample?

Thanks

Regards

DJ

With a GPIO supplied square wave applied to one side of the sense connection, between Vcc and common, and the other side to R3, which is being held at 1/2 Vcc by the op amp -- to me this appears to be symmetrical with no effective DC bias, as long as there is no other connection to the process being sensed

That is assuming the square wave is exactly 50% duty , or tweaked to negate any other parasitic effects.   You can get sometimes get closer to "exactly" 50% duty by using a flip-flop & driving it with 2x desired freq.

No desired accuracy has been stated.  The desired sensitivity has been alluded too (ohms/volt)

When in the dark remember-the future looks brighter than ever.

djoshi wrote:
Yes i am in pwm mode. This was to done to insure i get a good square wave as i can easily set the duty cycle. But i guess i could do the same with ctc and some software. So on a ctc interupt i enable adc to take one sample?

Not exactly. With compare reg A, you set the frequency, but do not enable the interrupt for compare match A. Set a delay with compare reg B and enable match interrupt for B. This interrupt will trigger a certain time after each rising and falling edge. Inside the ISR, check the PWM pin, if low, exit ISR, if high start an ADC conversion.

Edit: actually, I forgot the output is an inverting amplifier centered on mid-rail. So, on rising square wave edge, you do an ADC conversion and store min output value, and on falling edge, you do ADC conversion and store max value. The difference max-min will be your reading.

You can take readings only every other cycle or every 4 cycles or whatever is needed by ADC latency. You can also average many samples to get a more accurate result (oversample).

Last Edited: Mon. Jul 31, 2017 - 12:27 AM

Try this:

Generate a timer overflow at 4x square wave frequency.

Tick 1: Output low to high (in ISR software, NOT by direct PWM)

Tick 2: Start ADC conversion (in  ISR). Out of op-amp, this is LOW level

Tick 3: Output high to low (ditto)

Tick 4: Start ADC conversion (ditto). Out of op-amp, this is HIGH level

Tick 5: Start over - this is a new Tick 1.

Subtract ADC high reading from ADC low reading. This removes all dependency on bias levels, and such. You get a direct measure of signal PEAK-PEAK. Since operations are triggered by ISR, the ONLY variation that effects duty cycle is the ISR latency variation (which I think is about 6 MCU clock cycles). It should average to a consistent value over medium term and result in no net long term sensor bias.

This will work so long as 1/2 the square wave period is LONGER than the ADC conversion time. This requirement allows one ADC conversion to finish before the next one has to begin.

Compared to an earlier suggestion, this uses only ONE ADC channel with 2 readings every cycle of the square wave.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Mon. Jul 31, 2017 - 09:13 PM

Edit:

Listen to froggie #42

42 is always the answer, regardless of the question.

=======================

I sort of skipped this thread because I ham having dificulties in understanding the OP's explanation.

Hes talking about +/- 1V65 but there is now way anywhere in this circuit there is a negative voltage.

However when looking at the schematic I notice:

On pin 3 of the opamp there is a constant DC offset of 3V3/2 = 1V65

Opamp amplifies R4/R3 = 140k/1k = 140 times.

The circuit around the GPIO part (What does that do?) is nowhere near the 1V65 on pin 3 of the opamp.

So the opamp saturates with either Vcc or GND.

To get the output of the opamp out of saturation the DC voltage at the place of the  167k resistor must be within 12mV of the 1V65 on the non-inverting input pin 3.

Has this been mentioned in the #38 posts above or has everybody looked over it?

Did I interpret his question wrong?

Paul van der Hoeven.
Bunch of old projects with AVR's:
http://www.hoevendesign.com

Last Edited: Mon. Jul 31, 2017 - 09:29 PM

The 165K resistor appears to represent the lowest resistance offered by the sensor; the OP says that it will not be present when the sensor is present. The sensor resistance can be as high as 5M. This is what the OP appears to say in Msg #15 (and others). The way it is set up with 165K (or higher) at the input and 140K feedback, the gain should be slightly less (in magnitude) than 1 and should just barely keep out of saturation. With high load resistance, the op-amp will swing to within about 50mV of either rail.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Yes the 167K is for testing purpose, but the probes and water that will be measured will contribute the resistance.

I have not set up my ADC , and it seems to be working well.

When  i take samples of on 2nd tick, i am only taking 1 sample at moment, but will take more.

Thanks

Thanks

Regards

DJ

Paulvdh wrote:
Opamp amplifies R4/R3 = 140k/1k = 140 times.

140K / (1K + 167K) = 0.833 (where the 167K is used as a reference for the expected resistance of the solution)

And I did mention the voltage at pin 3 in post #4...

David (aka frog_jr)

I've made a quick scan of the thread.  I'd like to comment in general terms, as we have had "conductance probes" in several families of production apps over the past 15 years.

-- IME "single probe" systems, using the metal container as the common, are attractive.  But in practice one ends up with the equivalent of ground loops when multiple "vats" might be coupled, and performance is problematic.

-- We drive "dual probes" with a push-pull.  Indeed, unidirectional works -- until you plate your probes.

-- The resulting signal is put into an op-amp RMS converter.  That is the input to AVR8 ADC, non-differential.

-- IME it is very difficult to get "concentration" numbers, except in very controlled environments.  For example, say our target is 1% caustic.  If we have hard water, that might give a reading equivalent to half that concentration in non-hard-water.

-- Given the previous, most systems are run on an arbitrary scale, say 0-100.  The calibration is done with external means such as titration.  With given water and proper concentration, we might read "45" -- so that is the setpoint.

===========

One can get a simple "hardness meter" from China via eBay for a few bucks.  There isn't much inside it. ;)  [guess how I know]  If all you want is hardness or TDS, get one of those.

http://www.ebay.com/itm/TDS-Mete...

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

Input resistance is never as low as 1K. Minimum sensor resistance is 167K and as high as 5Meg.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Unless its shorted but do not think the condictivity of water with other substance will go beyond 6ec

Thanks

Regards

DJ

What is "EC" that you refer to?

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Electrical conductancy. I belive that what is used as a measurement

Thanks

Regards

DJ

That is not a term I know. Same as Siemens? I don't think so, give the values you quote. It must be ratio to the conductance of a standard sample.

Do you have a manufacturer and model for your sensor? I am interested in what you are using.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Mon. Jul 31, 2017 - 10:16 PM

Yes it can be converted to Siemens and ppm. I used ec so i could reference it to a selected resistance.

No sensor yet.

What values do you require?

Thanks

Regards

DJ

If you have no sensor, how can you specify resistance? It depends strongly on path lengths, cross-section areas, and such. One sensor is likely to be different resistance from other sensors for the same water conductivity. You cannot just convert conductivity to resistance without knowing the sensor geometry unless you are working with some sort of industry standard configuration.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Hi Jim

At moment i am using a test board to get my concept or simply to test the electronics are functioning.

Now that this is working, i will be creating the the PCB, which will be the sensor, that will produce a more accurate output.

Yes i agree that sensor to sensor there will be a slight change in conductivity, therefore there will always be percentage difference.

I am thinking of placing simple SMPT switch IC, that will isolate probe and connect a known resistance.

Using the known resistance i can work out by how much does each PCB in terms of percentage deviate from the one used during test. This percentage will be used to as the compensation / calibration factor.

During the initial test, i will measure various water samples with a variation in conductivity and against temperature. This will produce a conductivity value against conductivity for a certain temperature.

Using the same sensor, i will then place a known resistance under various temperatures, this will provide me with the ideal initial value prior to taking any sample. This will also be know as my calibration factor.

Thanks

Regards

DJ