Handler for L1 Cache Warning and Fault (SAMV71 - ARM-M7)

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Hello,

 

  I'm working on a project for a SAMV71Q21 device on a SAMV71 Xplained card.

 

  I want to add handlers for L1 cache errors. In the Datasheet (Table 13-1 - see below) I see that there are peripheral identifiers for CCW (64 - ARM Cache ECC Warning) and CCF (65 - Cache ECC Fault). 

 

  However, in the header file (samv71q21.h from Atmel Studio 7, version 7.0.1417), these don't appear to exist.

 

<snip>

  void* pfnXDMAC_Handler;  /* 58 DMA */
  void* pfnISI_Handler;    /* 59 Camera Interface */
  void* pfnPWM1_Handler;   /* 60 Pulse Width Modulation 1 */
  void* pvReserved61;
  void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
  void* pfnRSWDT_Handler;  /* 63 Reinforced Secure Watchdog Timer */
} DeviceVectors;

<snip>

  SDRAMC_IRQn          = 62, /**< 62 SAMV71Q20 SDRAM Controller (SDRAMC) */
  RSWDT_IRQn           = 63, /**< 63 SAMV71Q20 Reinforced Secure Watchdog Timer (RSWDT) */

  PERIPH_COUNT_IRQn    = 64  /**< Number of peripheral IDs */
} IRQn_Type;

 

  Can anybody provide some information about whether the SAMV71Q21 supports interrupts for L1 Cache ECC errors?  Is the header file just missing the definitions? Or does the hardware not support them.

 

Thanks,

 

->Adrian

 

 

Table 13.1 from SAMV71 Datasheet

citizen_adrian