I have a AtSamD21J18A which has a 1.00MHz oscillator as a clock source. I was thinking that
I would be able to use the FDPLL to generate 48MHz, use that as the CPU clock source and
feed it via one of the GClk output pins for external use.
The configuration seems OK to me in the Atmel Start config system - solid lines interconnecting
intended paths. However I can't get anything out of GClk outputs if those GClk blocks are
fed from the FDPLL. If I feed the GClk blocks from XOSc (the 1MHz source), I get an output,
but it is of course at the lower frequency.
Setting the multipliers on the FDPLL to a lower value (e.g. for 2MHz output) does no good.
More specifically, the FDPLL configuration widgets are set:
* Run in standby
* DPLL enable
* Lock bypass
* Clock divider=1 (for 2MHz)
ON DEMAND is not checked/set.
This is all in a simple LED-blinking program that seems to run fine.
Any hints or pointers to relevant documentation appreciated!