External SRAM & ATxmega128A1

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Background
I am working on a new board using the ATxmega128A1, but since I need more memory for this project it looks like I'm going to have to delve into the EBI. So will be attempting to add a 64Kx8 SRAM module to the 128A1.

On past boards, our primary development environment was building around AVR-GCC, and it looks like this one will be also.

Questions
1. In order to limit the wait states on the SRAM it looks like the 4 Port none ALE method is the easiest/quickest correct?

2. In the XMEGA A MANUAL, section 33.3, it shows the timing of the WRITE-NO-ALE sequence. If my Clksys is 32M and my Clkper2 is 64MHz, that should require an SRAM speed of 16 nsecs, correct?

3. In the XMEGA A MANUAL, section 33.3, it shows the timing of the WRITE-NO-ALE sequence to be 5 cycles of the Clkper2. I assume the last cycle is just the standard display-the-return-state, as with most timing diagrams. This should give me 2 Clksys cycles to do a write correct?

4. If I place the SRAM @0x4000, and leave the Stack @0x3FFF, it still looks like I do not have access to the entire 64K of the SRAM without using the long pointer registers. Is this TRUE?

5. I would like to put the .data and .bss sections in the SRAM, I assume I can use the .init1 section to program the EBI before the constants, and globals get initialized, correct?

thanks for your time

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Damn, no PORTL on the 128A1, so I can't use the 4 PORT EBI mode.

WTF? why is there documentation on the 4 PORT EBI mode when none of the processors support it?

3 wait states on the SRAM, thats really going to slow this down. Why oh why doesn't ATMEL give these bigger parts more ram?

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The Xmega128A1 Rev H and Rev G don't appear to mention EBI issues, which is a good thing.

That said, be sure to do a Forum Search on EBI as I recall at least one or two threads discussing EMI concerns.

JC

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DocJC wrote:
The Xmega128A1 Rev H and Rev G don't appear to mention EBI issues, which is a good thing.

That said, be sure to do a Forum Search on EBI as I recall at least one or two threads discussing EMI concerns.

JC

I did searchs for "EBI" and "EBI xmega", I didn't see the posts you were referring too. Or at least none that mention the xmega.

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This one , and perhaps some others.

JC

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DocJC wrote:
This one , and perhaps some others.

JC

Thanks JC.

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Also have a look at the Atmel AVR XPlain board. Its schematic is available on line, and it can act as a reference design for the two types (IIRC) of external memory connected to it.

JC

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DocJC wrote:
Also have a look at the Atmel AVR XPlain board. Its schematic is available on line, and it can act as a reference design for the two types (IIRC) of external memory connected to it.

JC

Good call, unfortunately we need to use SRAM, since we are going to memory map one of the peripherals. There is no support in the currently available chips for a mix of SDRAM and memory mapped peripherals.

The SDRAM uses up all of the control signals. :(

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I made a board using EBI and SRAM last year; using the three port mode with good results, but admittedly speed was not that important in that project. I remember that the appnote "AVR1312: Using the XMEGA External Bus Interface" was quite usefull for a quick summary of all the modes.

In regards to point 5, there are appnotes on the AVR32 for placing data in external SDRAM that probably will be analogue to this, as the tools are the same.

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dlmarti wrote:
3 wait states on the SRAM, thats really going to slow this down.
You should be able to operate with one wait state with reasonably fast SRAM. I've run the xmega128a1 with zero wait states using 10nS SRAM but I prefer set it to 1 wait state just to be conservative. The CPU speed in this case was 29.5MHz.

Don Kinzer
ZBasic Microcontrollers
http://www.zbasic.net

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dkinzer wrote:
dlmarti wrote:
3 wait states on the SRAM, thats really going to slow this down.
You should be able to operate with one wait state with reasonably fast SRAM. I've run the xmega128a1 with zero wait states using 10nS SRAM but I prefer set it to 1 wait state just to be conservative. The CPU speed in this case was 29.5MHz.

I mis-spoke, I should have said 3 cycles not 3 wait states.