I am working on a new board using the ATxmega128A1, but since I need more memory for this project it looks like I'm going to have to delve into the EBI. So will be attempting to add a 64Kx8 SRAM module to the 128A1.
On past boards, our primary development environment was building around AVR-GCC, and it looks like this one will be also.
1. In order to limit the wait states on the SRAM it looks like the 4 Port none ALE method is the easiest/quickest correct?
2. In the XMEGA A MANUAL, section 33.3, it shows the timing of the WRITE-NO-ALE sequence. If my Clksys is 32M and my Clkper2 is 64MHz, that should require an SRAM speed of 16 nsecs, correct?
3. In the XMEGA A MANUAL, section 33.3, it shows the timing of the WRITE-NO-ALE sequence to be 5 cycles of the Clkper2. I assume the last cycle is just the standard display-the-return-state, as with most timing diagrams. This should give me 2 Clksys cycles to do a write correct?
4. If I place the SRAM @0x4000, and leave the Stack @0x3FFF, it still looks like I do not have access to the entire 64K of the SRAM without using the long pointer registers. Is this TRUE?
5. I would like to put the .data and .bss sections in the SRAM, I assume I can use the .init1 section to program the EBI before the constants, and globals get initialized, correct?
thanks for your time