I am trying to learn how to design a DAC using PWM. Designing a low pass filter is new to me.
If you say you're not doing my homework for me I will be very pleased ... since I'm a couple of decades past that part of my life.
Assume I want a DAC with 10 bit accuracy using 16 bit timer.
* CPU (AT90USB646) frequency is 16 MHz.
* Using ten bit resolution 16-Bit timer
PWM Fundamental frequency (Fpwm)
= 16000000 / 1024 = 15625 Hz
Required minimum ripple (Astop)
= 6.02 * N + 1.76
= 6.02 * 11 + 1.76
= ~68 dB
First order filter (Fc)
= Fpwm / SQRT( ( 10 ^ Astop/20 ) ^ 2 - 1 )
= 15625 / SQRT( ( ( 10 ^ 68/20 ) ^ 2 ) - 1 )
= 15625 / 2500
= ~6 Hz
R (6 Hz) = 1 / (2 * PI * Fc * 10 uF)
= 1 / (2 * PI * 6 Hz * 10uF)
= ~2600 (2.7K) Ohms
So the low pass filter is R = 2.7K / C = 10 uF.
Am I applying these calculations properly or am I just not getting it?
My reference is Analog Circuits World Class Designs by Robert A. Peace. The chapter is called Working the Analog Problem From the Digital Domain by Bonnie Baker.
Also found helpful advice using Search from Jim Wagner :
You will need some kind of filter to smooth a PWM signal. It tends to be an RC, not JUST a capacitor. You want the filter corner frequency (for a simple RC) given by 1/2*pi*R*C to be lower than about 1/10 of the repetition frequency of the PWM (duty cycle) signal. Then, the output will be approximately Vcc*DutyCycle into a open-circuit "load". Generally, you want a minimum R of about 1000 ohms when the source of the PWM is a logic output.