I am using the AVR toolchain version 18.104.22.168, and AVR Studio V4.18 build 716 to compile a C program for the ATtiny10 family.
I am currently compiling for the ATtiny10 (instead of the desired ATtiny4) as the generated code is much bigger than expected and fits onto the ATtiny10 when optimised.
There are some strange issues which I am seeing that don't seem to make any sense.
I was trying to simulate the code (using the AVR Simulator 2 and ATtiny10 option) and noticed that the location of the variables was outside of the memory space. The compiler says that only 11 bytes of the Data section are used, but it is placing the variables in a strange place.
The variables appear to be placed starting at 0x0060, which is not the SRAM location, they should be placed starting at 0x0040 - 0x005F. This is seen my mousing over the variable when debugging.
I then had a look at the .map file that is being generated, and it has the following close to the start,
Memory Configuration Name Origin Length Attributes text 0x00000000 0x00002000 xr data 0x00800060 0x0000ffa0 rw !x eeprom 0x00810000 0x00010000 rw !x fuse 0x00820000 0x00000400 rw !x lock 0x00830000 0x00000400 rw !x signature 0x00840000 0x00000400 rw !x *default* 0x00000000 0xffffffff
which bears no resemblance to the memory mapping of the ATtiny10 family. If you only look at the lower two bytes of the data address it is equal to 0x0060.
I then looked at the .lss file which also indicates that the variables are accessed in memory which does not exist, e.g. mode is stored at 0x0064.
mode ^= 1; // Invert the mode (only on or off) 382: 90 91 64 00 lds r25, 0x0064 386: 81 e0 ldi r24, 0x01 ; 1 388: 89 27 eor r24, r25 38a: 80 93 64 00 sts 0x0064, r24
I have also noticed that some optimisations are not being performed as expected (with -Os). There are some places that I use sfr |= _BV(bit), and that is not being optimised to a sbi (or cli) command. Certain places it does, others it does not, e.g. (optimised code)
// Disable the pin change interrupt PCICR &= ~(_BV(PCIE0)); 60: e2 e1 ldi r30, 0x12 ; 18 62: f0 e0 ldi r31, 0x00 ; 0 64: 80 81 ld r24, Z 66: 8e 7f andi r24, 0xFE ; 254 68: 80 83 st Z, r24 [snip] PCICR |= _BV(PCIE0); 27a: 20 91 12 00 lds r18, 0x0012 27e: 21 60 ori r18, 0x01 ; 1 280: 20 93 12 00 sts 0x0012, r18 [snip] TIMSK0 |= _BV(OCIE0B); 2e8: 5a 9a sbi 0x0b, 2 ; 11
I am a bit unsure where things are going wrong - any ideas as to how to resolve this?