atmega32u4's "six" programmable endpoints

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I'm working with some code that sets up USB communications on an Atmega32u4. According to the specs, that has "six" endpoints. Studying existing code and USB descriptor tables, it appears that at least some things working on some USB chips will use the same "endpoint number" for both input and output, except that one of them has a direction bit masked in. (So, for instance, you might have 0x02 and 0x82, where 0x80 is ENDPOINT_DIR_IN.)

 

This seems to work on at least some hardware.

 

What I can't figure out from any of the specs I've read is: When they say "six programmable endpoints", does having two endpoints in the USB device report, one on 0x02 and one on 0x82, count as two of the six endpoints? Will it work as-expected? The endpoint configuration register stuff is confusing to me and I have not yet understood how it's supposed to work.

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I got USB working on the Xmega and I'm still confused about that.

 

Here's what I know, at least about the Xmega USB.  At least sometimes, some people consider endpoints in pairs.  For CDC, I use 3 pairs.  In the USB registers there is a place to put the maximum endpoint number.  I use 2 (and it works).  I suppose that is for endpoint pairs 0, 1, and 2.  The first pair is used for control out and control in, in that order.  I think this is required by USB.  The second pair has the first one disabled and the second one is for "interrupt in".   The third pair is used for user data out and user data in.   

 

Note, I always make the out endpoint be the first of the pair and of course the in endpoint is the second one of the pair.   I don't know if this is required.

 

I did learn that the user data out and in endpoints don't have to be members of the same pair.  This configuration is required to use the "ping-pong" feature which supposedly increases the throughput.

 

In the Xmega, the endpoint registers are in RAM rather than I/O registers.  They had to enhance the RAM to pull this off.  Is this true of the Mega USB also?

 

I just saw this in the Xmega manual USB section:

 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints

Based on this terminology, I think you have 3 pairs of endpoints.  (6 endpoints total).

 

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Maybe RAM wasn't enhanced.  The instruction set was enhanced.  The Xmega with USB now has instructions that can flip a bit in RAM without separate read-modify-write instructions.  

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That does sound like the 32u4 may well only have six endpoints available. (Note that it can definitely use more than three addresses, you can have things on all of 0-5).

 

 

It sounds to me like "16 pairs" and "31" implies that the xmega has the fixed/unchangeable endpoint 0, and can then have pairs on endpoints 1..15. So it may be that the 32u4 can only "really" have five endpoints other than control, but on the other hand, I've seen code that appears to be defining six past the control endpoint and still working.

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I noticed that "31 endpoints" thing and I don't have any explanation for it.  I believe the first 2 endpoints have to be the control endpoints, out and in.

 

I also see this in the manual.

The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of
31 configurable endpoints and one control endpoint.

I kind of figured that, and I'm glad to see it in print.  I'll go one further and say the first endpoint has to be the output (from the host) endpoint.  I could be wrong but I don't see anywhere the endpoint registers indicate in or out.  I don't see anything in the endpoint registers that contain addresses either.  It's all in Atmel's imagination.

 

The endpoint registers have to be in an array.  When an interrupt occurs that applies to one specific endpoint, it gives us an index into the array that allows us to know which endpoint it applies to.  The exception is the setup packets that come in on the first (control) endpoint.  In this case, the interrupt status indicates it's a setup interrupt.

 

Here are the endpoint registers for one endpoint.  No mention of address or in/out direction.  Aha, now I see something.  Indeed the IN endpoint is the second of the pair because it's address is 8 greater than the OUT endpoint.

 

 

Last Edited: Wed. Dec 6, 2017 - 10:28 PM