I have I2C software that is working fine as a ATtiny85 USI I2C Master.
I observe while in AS7 assembler simulation mode for a Master Tx, the USIDR clocks out (shifts left -> B7)
3 bits, for 3 pairs of +/- clock edges.
After that it, no further shifting is observed.
USICR is set to 0x2A (USIWM1 = 1, USIWM0 = 0) for the entire program.
Bit PB0 (SDA) in the DDRB remains constant for a complete Master Tx/Rx cycle.
And something similar happens while in AS7 assembler simulation mode for a Master Rx, the USIDR clocks
in (shifts left -> B7) 5-6 bits, for 10-12 pairs of +/- clock edges.
Any thoughts ?
Has anyone else experienced difficulties with ATtiny85 I2C USI simulation ?
Merry Christmas & a happy New Year.