ADC Puzzle

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Greetings -

 

I am adding solar power to my Mega328P-based accelerometer. The accelerometer uses a nice little switch-mode boost supply with very low quiescent current and which operates down to 0.9V input with 3.3V out. Thus, I can easily measure the 1.5V nominal battery voltage with the ADC using Vcc as reference. Vcc seems quite stable. 

 

To sort out what happens when the battery voltage drops below 0.9V and the switcher begins operating improperly, I decided to add a Vref measurement. 

 

My measurement algorithm uses a state machine. The whole system is driven by accelerometer data ready signals at 100Hz and sleeps after processing is complete until awakened by the accelerometer. The algorithm waits some defined number of trigger cycles, then turns on the ADC and makes the first measurement (on the battery channel). On the next accel trigger, that measurement is discarded, and another one is started. The next trigger saves the second ADC reading, changes the channel to read the bandgap reference, and starts a new conversion. The next trigger reads and discards that measurement, and starts a new one. On the next, the reading is saved and the ADC is turned off. The final accel trigger causes the two values to be written to a uSD card. 

 

I have extracted the ADC data from the log file. Here is the data from a 20 second repeat interval for about 5 minutes. The first column the record type, the second is the battery, and the third is the reference. The numbers are the base-10 representation of the 10 bit ADC output. In the plot, below, blue is battery voltage and green is reference. The consistency of the battery reading and the variation of the reference is quite puzzling. Yes, ARef has a bypass cap. The reference seems, almost, to have a defined pattern. 

 

I can live with this, being mostly interested in the battery voltage. But, if anyone has any insight on what might be going on, I'd love to read what any of you might have to suggest.

 

Thanks

Jim

 

recordtype,battery,reference 

V,466,339
V,466,339
V,466,371
V,466,340
V,466,340
V,465,370
V,466,340
V,466,339
V,467,376
V,466,340
V,466,339
V,466,339
V,466,339
V,466,339
V,466,340
V,462,372
V,466,339
V,466,339
V,466,370
V,466,340
V,466,339
V,466,369
V,465,370

 

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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I think that it is the following.

as your battery voltage drops below the safe operating point of your switcher the switcher no longer is capable of producing a solid 3,3V.

I do not read that you have taken another reference voltage so I Asume you use the supply voltage as reference for your battery measurement. 

Normally when your ADC voltage drops the ADC output stays the same and so does the reference.

Because your reference voltgae is also dropping, the ADC-MAX is no longer at 3,3V but lets say at 3,0V this means that with the same input voltage you will end up with a higher ADC value

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what else go on on that board?

For me it looks like there are two different power loads. (are there a RF Tx that sometimes is on or something like that?)  

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Writes to the uSD card take extra power every time the buffer fills. That might do it. Indeed.

 

Thanks

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Thu. Feb 8, 2018 - 03:38 PM
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as your battery voltage drops below the safe operating point of your switcher the switcher no longer is capable of producing a solid 3,3V.

Except that the switch reportedly can provide a solid/clean 3.3V with as little as 0.9V in.  The reported 466 corresponds to 1.5V in.  Surely the switcher output is solid/clean with that input?

 

Writes to the uSD card take extra power every time the buffer fills. That might do it. Indeed.

In my experience, with the few SD loggers I've built, that is a definite concern.  If at all possible, all sampling should occur under the same load conditions.  That is, if you app has high-current loads, the sampling should occur when those loads are not active.  Sample when you know the SD card is idle.

 

I didn't see the graph you mentioned in #1 (maybe a script blocker on my end?).  I prepared this one:

 

 

That's quite a jump in Vbg.

 

I don't see a strong correlation.  For some of the spikes on Vbg, there is a dip in Vbatt.  For others, there is a spike.  For still others, there is no change.  Here is the same data with auto-scaling on each trace individually, so you can see correlation better:

 

 

So the correlation is strong temporally, but not w.r.t. swing i.e. neither strong positive nor strong negative correlation.  To me this suggests a yet-to-be imagined/discovered underlying cause.

 

Note that the variation on the Vbatt channel is (with one exception) just +/- 1 or 2 LSB, which is into the noise floor of the ADC itself, so inferences based upon this column of the dataset may be suspect.

 

I would inclined to scope Aref and AVcc as the logfile is accumulated.  If you can then correlate the scope trace with the log file timestamps, you may get an answer.

 

 

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"Read a lot.  Write a lot."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

Last Edited: Thu. Feb 8, 2018 - 04:59 PM
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Also, battery voltage should creep down like a glacier...why not also apply some slow averaging?

 

similar to: Vnew=(15*Vold+Vsamp)/16

When in the dark remember-the future looks brighter than ever.

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Yes, clearly I need to look at Vcc with a scope. That would resolve it OR create new questions. 

 

At this point, I think that I will just let it do what it is doing. Its a retrofit on a production board and it is already painful to add the Aref bypass cap and the ADC input connection. But, I will look with the scope just to understand what is happening.

 

Thanks and cheers,

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Assuming Vbg is not actually fluctuating (while it is +/-10% for any given device, it shouldn't vary more than 1 or 2mV over the range 2.0<Vcc<4.5, and no more than 10mV from 20C to 40C.  You're seeing 100mV swings from one sample to the next around those spikes.  While your samples are 1 second (?) apart, that still represents a massive change in Vbg which can't be explained by temperature, nor by a wildly swinging Vcc >>in and of itself<<.

 

However, as noted, with AVcc as your reference, changes in Vcc would result in errors when reading Vbg.  An observed spike of +100mV on Vbg would require a coincident droop of about -300mV on Vcc (for Vcc=3.3V).  So if a sustained heavy load were to cause the output of the switcher to droop to 3.0V, you might see Vbg spike like your log file shows.  However, I would expect Vbatt to show the exact same kind of spiking.

 

Here's the catch, though.  If the battery's actual voltage were constant, I would expect the same spiking as just mentioned.  However, if a heavy load is causing the switcher output to droop, this also presumably is coincident with the switcher placing a heavier demand on the battery.  As a result, Vbatt would actually drop.  That drop, combined with the drop in AVcc/Aref would tend to cancel each other out.  The drop in the actual battery voltage would tend towards lower ADC sample values, while the drop in AVcc/Aref would tend towards higher ADC samples.

 

It does seem a little too convenient that these two effects would so completely cancel each other out as your log file seems to show.  Only a DSO trace of Vbatt and the switcher output would show you if this is actually happening.

 

Another option is to use Vbg as a reference instead.  Unfortunately, Vbatt above 1.1V would saturate at 0x3FF, unless you used a voltage divider.  That may not be a terrible idea, though.   A 1M/1M divider would draw 750 nA, and have a negligible impact on battery life (a typical AA with 2700mAh would last 410 years at that rate).  While this is way outside the nominal 10K input impedance recommendation, that really only applies to fast-moving signals.  If you are measuring more than one channel in round-robin, you may get inaccuracies unless you allow the ADC S/H cap enough time to settle after switching to the Vbatt channel before initiating the conversion.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"Read a lot.  Write a lot."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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that really only applies to fast-moving signals

I'm not sure a 1M / 1M divider, without a external cap, would be accurate.

 

I suspect that the internal sample and hold cap gets 1, (or whatever), clock cycles in which to capture the presented voltage.

The 500K external impedance, (1M//1M), will form a voltage divider with the ADC's internal impedance.

 

I think one would have to look at the internal sample and hold cap's gate interval to see just how many time constants one is charging the cap, and hence its "accuracy".

 

Clearly some time digging in the data sheet and a few calculations will reveal if this is an issue at all, or not, but I'd not take it for granted.

 

JC

 

 

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The bandgap reading has a huge bimodal distribution (8%), and it's the one that should be the steadiest!  I wonder if , whenever switching channels to bandgap (chan14), the 1st reading is really being discarded?   This also assumes the adc ref is kept steadily selected as Vcc , since, if not, the aref cap needs time to settle.

You could quick test this out by simply temporarily changing your battery reading chan to also be the bandgap (chan 14)...so no channel changing to effect things.  Hopefully the two columns then match up & also eliminate the variations. 

 

 A multimeter on Vcc might easily tell a good story.  On a scope you might see a relatively small jump, so a close look is needed.

When in the dark remember-the future looks brighter than ever.

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I'm not sure a 1M / 1M divider, without a external cap, would be accurate.

In my experience, it is.  An external cap can be helpful in a noisy environment, or when sampling more than one channel in round-robin.  The S/H cap will 'sip' (as Lee has often said) from the channel's cap.  If only ever sampling one channel, the S/H cap will always be connected to the output of the voltage divider (except during the 13 ADC clocks while the conversion is in progress), so you don't need an external cap to quickly change the S/H cap's state-of-charge from the likely different state it was in when it disconnected from the previous channel.

 

If Jim wants to continue a round-robin schedule of measuring Vbatt and Vbg, then a cap might indeed be necessary, and yes a 1M/1M divider would likely have too high an impedance to feed that cap and the S/H cap as they swing between the two voltages.  Note, however, the he's already discarding the first sample, and samples seem to be taken about one second apart.  So the divider is connected to the S/H for one full second before the 'real' sample is converted.  With a 14 pF S/H cap and a 1M input impedance, the TC is 1E6 x 14E-12 = 14us.  The S/H cap will settle to within 1 LSB in about 7 TC [ln 1024], or about 100 us.

 

I suspect that the internal sample and hold cap gets 1, (or whatever), clock cycles in which to capture the presented voltage.

I has >>at least<< 1.5 ADC clock cycles.  At 125 kHz, that's 12us.  Not enough for the 100 us I calculate above.  However, the S/H cap is always connected to the input MUX, >>until<< 1.5 ADC clock into a conversion.  That is, however long to wait between changing the MUX and initiating the conversion, the S/H cap remains connected to the input, and follows it [subject to the TC of the input path].  If you want to convert as fast as possible, then yes, the S/H cap has only 1.5 ADC clocks to ramp to the input.  Therein lies the reasoning behind the 10K input impedance spec quoted in the datasheet.

 

I did a lot of investigating into the behaviour of the ADC a few years ago.  There's at least one thread kicking around here...

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"Read a lot.  Write a lot."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

Last Edited: Thu. Feb 8, 2018 - 09:46 PM
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As a note, the state machine steps through its states every 10ms. There is approximately 20 seconds, in this test, between measurement cycles - will normally be an hour. 

 

The uSD card is written to AFTER the last reference measurement. There are OTHER writes to the uSD card and it appears that the physical page write occurs maybe once every 10*10ms. 

 

Clearly, I need to do some oscilloscope validation, here.

 

Thanks for everyones ideas and suggestions!

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Also note, if the ADC is turned off, the bandgap takes a some time to resume operation, if not already on via other settings.  70us is a pretty long time for a processor.  (This is not likely an issue with your sampling arrangement).

 

Bandgap reference start-up time VCC=2.7 TA=25°C 40 to 70 μs

The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given

in ”System and Reset Characteristics” on page 312. To save power, the reference is not always turned on. The reference

is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses).....(likely you have this enabled, hence the bandgap is always on).

2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).

3. When the ADC is enabled

When in the dark remember-the future looks brighter than ever.

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Right on bandgap after turnon. It is turned off after every measurement sequence, but then measures the battery first with no obvious artifact in that measurement.

 

It is turned on, then takes 30ms for the actual measurement that is in the table in msg #1. External cap on Vref is 0.1uF but that SHOULD be filtering the Vcc reference. I think that I had better double check the code where the input changes from battery to reference to make sure that everything is as it should be.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net