ADC noise - PCB vs Breadboard...

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#1
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Hi,

I've been using an ADC to monitor 3 voltages and my timer that occurs every 1 millisecond kicks off the beginning of the 3 conversions. I add up 500 of these and divide by 500 to get an average.

Something interesting is that in the breadboard environment it seemed to work better, and had better accuracy.

When testing it on a finished PCB however I noticed something odd, on the PCB it would "step" into a value and stay there even when the meter showed voltage was dropping steadily in a linear way.

I freely admit I am trying to get more accuracy than the 10 bits would suggest, and on the breadboard my averaging was doing a good job.

Last night I ended up making some test code to run on the breadboard vs the pcb and it proved what I thought might be happening. It would count up each ADC value reported during the number of conversions (1000) and keep track of how many of each result. It could display up to 10 of these on the lcd display.

Sure enough the breadboard was very noisy with all ten spots filled all the time. ADC values ranged from say 769 to 781.

My theory was that on the PCB, that I would be getting the accuracy I wanted when it was between ADC values and the duty cycle between them was providing the accuracy. But, with all the noisy results on the breadboard I wondered what I would get.

After loading the same code on the PCB, sure enough I only got 2 values reported. As the voltage dropped, you can clearly see the duty cycle (or number of times reported) moving from one ADC value to the next.

The "step" where the value would lock into a value for awhile is coming from the zone when only one ADC value is reported 1000 times because we don't know if those 1000 times are all at the top part of that value or the bottom part.

Yes, I know I was expecting more than the 10 bits can deliver, but I sure like the extra accuracy that can be obtained when it is in between ADC values.

It turns out that about 33% of my range is in between ADC values (and more accurate) and the other 66% are not.

Do some designs introduce random noise in an ADC circuit to get more accuracy?

What about a software method?

I am using a 100nF cap in the voltage divider now. If removed and there is more noise, might it actually be more accurate without it! ?

Thanks,

Alan

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Yes, introducing noise can improve ADC performance. It has to be the right sort of noise, though.

Leon Heller
G1HSM

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Hi,

I lifted the cap on my pcb to see the results, and this did add a little noise, instead of one or two adc values flowing into each other, I now have 3 or 4.

What is odd is that it doesn't flow how I'd expect:

adc-cnt adc-cnt adc-cnt
460-664 461-171 462-165

Note that the highest count is adc value 460, with 664/1000 samples. Then the next highest has 171, then the next 165.

I would have expected the largest number to be in the middle like this instead and watching the left increase as the right decreases (falling voltage).

what I expected, but didn't get:
adc-cnt adc-cnt adc-cnt
460-171 461-664 462-165

Thanks,

Alan

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1) What is your ADC clock value?
2) How much drive is on your input signal?
3) Is there >>no<< ripple on your (A)Vcc, Gnd, ref, and input signals? (If you say no, I'll find it hard to believe)
4) What results do you get when adding a small cap to Gnd near each input pin?
5) Are the digital and analog parts of your board properly separated, decoupled, and the like for proper analog design?

Re 3) & 4): Do the readings change when you put a 'scope probe right on the AVR pin?

You can put lipstick on a pig, but it is still a pig.

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alank2 wrote:
... the voltage divider ...
What is the equivalent signal source impedance seen by your ADC's input? From memory (please correct me if you know otherwise) it needs to be less than 10K to meet the ADC's 10 bit accuracy spec.

Cheers,

Ross

Ross McKenzie ValuSoft Melbourne Australia

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Hi,

#1 - 128K

#2 - 56.2K resistor between my voltage source and the ADC pin. There is also a 10.7K resistor to ground. Yes, I know this is too high and above 10K. One thing I am monitoring is a battery and I don't want to drain it excessively.

#3 - I agree, there is always SOME ripple. I am using a 330uF main cap and also a 47uF ceramic cap because it seemed to tame noise a bit.

#4 - See my original message above. With a 100nF cap, it is so clean and error free that it freely flows from one ADC value to another, and it can be the same for 1000 conversions in a row. When I pulled the cap to introduce some noise, I got 3 or 4 instead of 1 or 2 values returned for 1000 samples. The odd thing was that the 3 or 4 did not look linear as I would have expected.

#5 - I think I am ok on this, but I'm no expert so here is the schematic:
http://www.sadevelopment.com/pressmonitor/sch.pdf

Thanks guys!

Alan

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The voltage divider is not to high in impedance. With 50 K and 10 K the impedance is about 8.3 K. Even a lower current. e.g. 10 times lager resistors, is possible with a capacitor ( > 15 nF) at the input. But then you might need an extra "noise"-source.

The differential nonlinearity (DNL) of the ADC is not very good. So the interval for the ADC values are not garantied to be absolutly equal. Most intervalls are quite good, its usually only those where the higher bits change that are off.

The extra variations you get are probably not due to noise, due to a deterministic signal (e.g. power line frequency or harmonics). This signal may be asysmetric to cause the slightly odd looking distribution.