Using bus-keeper pins as latch in power-save modes?

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Hi,

I was wondering if anybody has had enough experience with using the bus-keeper configuration of I/O pins and whether they could be used to latch to a logic level while the Xmega is in a power-save mode.

I need to keep a separate power supply enabled continuously for a set period of time, even while the Xmega is in the power-save mode. I don't really want to keep the other power supply enabled all of the time, since the quiescent current is too high for this battery-powered application.

I could just design in a latch, but if the bus-keeper can do the same job, I would prefer it as simpler approach.

Thanks!

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Buskeeper is an intelligent pullup/pulldown, when the pin is in input mode and Activation of pullup or pulldown depends on pin state in output mode. In Sleep modes each output pin holds its state, but what do you mean about using an input pin as an output latch?

Ozhan KD
Knowledge is POWER

Last Edited: Thu. Mar 31, 2011 - 08:20 PM
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electronic.designer wrote:
Buskeeper is an intelligent pullup/pulldown, when the pin is in input mode and Activation of pullup or pulldown depends on pin state in output mode. In Sleep modes each output pin holds its state, but what do you mean about using an input pin as an output latch?

Thank you for the response.

I wanted to use the pin as an output to the enable line on an external power supply, that way when the Xmega enters a sleep mode, the pin would hopefully stay at the same level that I had set it to while the Xmega was still active.

So essentially it would act like a d-type latch and keep the external regulator either enabled or disabled independently of the Xmega sleep state.

Thanks.

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I would think this would work. The sleep function is used to stop the clock and shut off peripherals, but I/O states are not mentioned anywhere. Since buskeeper is simply a weak pull up/ pull down the configuration should stay the same during sleep.

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Why not just use any old I/O pin? They should all hold their state over sleep mode changes.

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schtevo wrote:
Why not just use any old I/O pin? They should all hold their state over sleep mode changes.
Thanks Schtevo,

I was under the impression that the IO would be tri-stated once a low power sleep mode was entered. If I can rely on the pin state being maintained through sleep and wakeup, that would be perfect.

I read AVR1010 and that seems to indicate that GPIO are not affected by the sleep mode, so that is encouraging.

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Quote:

I was under the impression that the IO would be tri-stated once a low power sleep mode was entered

Whatever gave you that idea? They are static latches and retain state whether the CPU clocks or not. The only things to tri-state IO are setting their direction register to input with no resistors enabled or holding the chip in _RESET