Need SRAM timing for synchronous system

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I am attempting to interface one of our custom VLSI chips
to the SRAM address/data bus available in the AT90S8515.
However none of the timing parameters given for the SRAM
interface references the clock and our custom VLSI is
synchronous. Does anybody know where a timing diagram
referencing clock edges can be found? Or, alternatively,
has anybody faced the same problem and developed their
own timing dragram from analyzing scope traces?

HAL

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Hi!

Have you had a look at Figure 68: External RAM Timing in the datasheet? It hasn't got anchor reference, but there's edges and cycles :) It's on page 82 of the sheet available on this site. It's a bit tricky to find if you're looking at the "External RAM" section...

If that's not enough, I think you have to use a scope. I'm intrigued: Why does the VLSI chip use this interface? Is it because you've used up all the others (UART, SPI)? Probably seems like a stupid question, but I'm curious and not afraid to show it! ;-)

Corinthian

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Yes, figure 68 on page 82 is what I was looking at. Although the clock
waveform and specs for it are shown, there is no reference in any of the
SRAM waveforms below that refer to the clock.

I did try some paper analysis though. As drawn, one might conclude that ALE
rising edge is caused by the falling edge of the clock in T1. Since there is
nothing that obviously "causes" the falling edge of ALE, one might conclude
that its width is set by on-chip logic delays (a "one-shot" mechanism).
However, elsewhere, the width is specified as 1/2 the clock period less 30nS
so its not an on-chip one-shot. One might then conclude that the RISING edge
of the clock causes ALE to turn on and the falling edge turns it off. That's
probably what's happening and the turn-on delay is 30nS longer than the turn
off delay. However that means (if the drawing is reasonably accurate) a
whopping 62nS delay from clock edge to ALE. Add a 50% tolerance on such a
delay and that's a lot of uncertainty. So probably the drawn relationship
between CLK and ALE (and by inference the rest of the diagram) is not
accurate at all.

I will probably simply wire up an 8515, a latch, and an SRAM; write a simple
program that scans through the SRAM incrementing each location, and scope it
out at different clock frequencies. Varying the supply voltage some would
give an idea of the variance I can expect. I should be able to do this
before the PCB layout for the real project gets too far along.

As to why I need to interface something via the SRAM interface, what is being
interfaced is a custom sound synthesizer chip. This, like a lot of interface
chips, has a set of registers that one reads and writes to specify
parameters, give commands, and receive status very quickly. This particular
chip has 32 sound channels and each has about a dozen 24- and 32-bit
registers (which can be written and read a byte at a time). The registers
are such things as frequency, amplitude, 2 filter coefficients, 3 sound
memory pointers, and so forth. The application needs to update most of these
every 20 milliseconds while notes are playing. A parallel bus-type interface
is the only way to do this fast enough.

The sound chip can deal with an asynchronous clock (by enabling its on-chip
synchronizers) but it responds faster if they are bypassed. Since the SRAM
interface has at most one wait state which is barely long enough without the
synchronizers, I must use the synchronous interface option. T'would have
been nice if one of the I/O pins could optionally be used as a RDY or DTACK
input for external bus interface devices.

HAL

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Hi!

Impressive design! Sorry I couldn't help you... You're out of my league :) It seems like you've found a way, though.

Corinthian

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