I might (???) have encounterd a problem with timer1:
I use timer1 in the compare capture mode. Setting the prescaler to "8" and given, the compare match would occur at "3", the counter would generate the following sequence:
00000000 11111111 22222222 3 call ISR
as in, the ISR would be called after the 25th cycle!?
After the occurance of the first overflow - and for all future events - the counting pattern would be:
0000000 11111111 22222222 3 call ISR
and that's ONE cycle less.
Am I right or wrong??? Does it really mean a "problem". I'm generally interessted in solving that problem and addressed it to Atmel directly via their internet page, but no response (yet?)
Your opinions will be appreciated!