Continuing the discussion which ended the following topic: http://www.avrfreaks.net/forum/p...
I am facing an issue with the AT32UC3C0512 processor for some weeks now;
I am building an algorithm which controls a power converter (HF cycle by cycle).
The converter should be able to run at switching cycles up to 200kHz.
I make use of as many hardware peripherals as possible to minimize software dependency.
Unfortunately due to the control principle I have to handle 2 interrupts (based on pin changes) during each HF cycle.
It turns out that the handling on an interrupt (which is based on a rising edge of designated pin) takes 100+!!! cycles before it is executed.
I check this by toggling a pin when entering the function (and comparing this with a scope to the timing of the original input signal).
I am sure the controller runns at 64mHz but still the delay can be up to 2us (which I see happening twice in each HF cycle)!
The delayed timing is very consistent.
I make use of ASF to configure the controller and peripherals.
The only thing I can conclude is that there must be a HUGE ASF overhead in the interrupt handling..
But 128 cycles just feels extreme and highly unlikely!
Is there some option (debug or optimisation) I am missing which maybe reduces the amount of data put on stack>?
Can I see or check what the processor is doing duing these cycles?
What can I do?
Please help; I have spend days looking for an answer!