8 bit timer TCNT register preloading not working as expected

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Hi,

 

I have been trying to generate different frequency and duty PWM waveforms by injecting values into TCNT register during bootup and inside the timer overflow vector ISR. My expected frequency( as per my timer calculations) and my received PWM output for the code is fine upto certain TCNT value(approx TCNT0=180). Once I set the TCNT0 register above approx 180. I am getting a frequency that does not match up with my calculations. I would like to know if this is due to some sort of limitation with the 8 bit timer OVF vector ISR itself.

 

Thanks 

Vasanth

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Last Edited: Fri. Jan 12, 2018 - 04:06 AM
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Let's see the code.  Preferably a complete test program.  Tell toolchain, version, and clock speed.  Show schematic.  Tell how you are testing.  Tell what you expect to happen, and what >>is<< happening.

 

If e.g. the timer is running at /1 then if you are doing an ISR every timer cycle and if servicing your ISR takes more than 75 cycles, then indeed you will not be able to "keep up".

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If e.g. the timer is running at /1 then if you are doing an ISR every timer cycle and if servicing your ISR takes more than 75 cycles, then indeed you will not be able to "keep up".

 

 

Thanks for the hint. I am using 8mhz clock without any prescaling. My timer0 overflow ISR  works after disabling the timer 1 Overflow ISR. I also managed to get things working without changing the Timer1 ISR by using Timer0 compare match A and compare match B ISR to generate my PWM on and off seperately. (previously I used overflow timer to do that)

 

 

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...by injecting values into TCNT register during bootup and inside the timer overflow vector ISR

Note that if there are other blocking interrupts already in progress, your IRQ adjustment/reloading of TCNT timing values will be delayed & obviously affecting the timing.  One way is to make the other IRQ's interruptible, but that is fraught with some danger--care must be used.   Another reason to keep IRQ's shrt and sweet (so the delay is minimal).

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