AS7 Simulation ATtiny85 USI I2C USIDR ClkIn ClkOut

Go To Last Post
2 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I have I2C software that is working fine as a ATtiny85 USI I2C Master.

 

I observe while in AS7 assembler simulation mode for a Master Tx, the USIDR clocks out (shifts left -> B7)

  3 bits, for 3 pairs of +/- clock edges.

 

After that it, no further shifting is observed.

 

USICR is set to 0x2A (USIWM1 = 1, USIWM0 = 0) for the entire program.

Bit PB0 (SDA) in the DDRB remains constant for a complete Master Tx/Rx cycle.

 

And something similar happens while in AS7 assembler simulation mode for a Master Rx, the USIDR clocks

  in (shifts left -> B7)  5-6 bits, for 10-12 pairs of +/- clock edges.

 

Any thoughts ?

 

Has anyone else experienced difficulties with ATtiny85 I2C USI simulation ?

 

Merry Christmas & a happy New Year.

 

 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0
Further investigation into simulating a ATtiny85 using the I2C USI using AS7 suggests the following:

Code and notes

        ; USI will not work in I2C mode without the following two commands
        ; Disables the receive logic in transmit mode from seeing a START condition
        ; Set SDA = 1 and SCL = 1

        sbi   PORTB, PB0                 ;(2) Enable internal pullup resistor on SDA
        sbi   PORTB, PB2                 ;(2) Enable internal pullup resistor on SCL

        sbi   DDRB, PB0                  ;(2) SDA -> Output
        sbi   DDRB, PB2                  ;(2) SCL -> Output

        sbi   USIDR, 7                   ;(2) PORTB.PB0 AND USIDR.B7 determine SDA output.
                                         ;        1     AND     1 

        ;USISIE = 0, Disable Start Condition Interrupt
        ;USIOIE = 0, Disable Overflow Interrupt
        ;USIWM1 = 1, Enable Two Wire Serial mode, Port pins either Inputs or Open Drain outputs
        ;            "Hold SCL down" when Start Condition detected
        ;USIWM0 = 0, Disable Two Wire Serial mode with "Hold SCL down" when USI counter overflows
        ;USICS1 = 1, Next three bits define how clock works.
        ;USICS0 = 0, External clock, USIDR shifts on positive edge only
        ;USICLK = 1, Overflow counter triggered on positive edge of external clock
        ;USITC  = 0, Disable Toggle SCK pin
        ldi   XL, (0<<USISIE)+(0<<USIOIE)+(1<<USIWM1)+(0<<USIWM0)+(1<<USICS1)+(0<<USICS0)+(1<<USICLK)+(0<<USITC) ; (1)
        out   USICR, XL                  ;(1)

        ;USISIF  = 1, Clear Start Condition Interrupt & clear start detection hold of SCL line
        ;USIOIF  = 1, Clear Overflow Condition interrupt flag, release the counter overflow hold of SCL line
        ;USIPF   = 1, Clear Stop Condition flag
        ;USIDC   = 1, Clear Data Output Collision flag
        ;USICNT3 = 0, Clear all bits B3 - B0 of USI counter
        ;USICNT2 = 0,    effectively setting up counter to write 8 data bits
        ;USICNT1 = 0,    over 16 clock cycles
        ;USICNT0 = 0,
        ldi   XL, (1<<USISIF)+(1<<USIOIF)+(1<<USIPF)+(1<<USIDC)+(0<<USICNT3)+(0<<USICNT2)+(0<<USICNT1)+(0<<USICNT0) ;(1)
        out   USISR, XL                  ;(1)

        ; Notes on Single Stepping code involving PORTB and USI Interface
	;-----------------------------------------------------------------
	;
	; Simulation of USI Data Register (USIDR) content:
	;-------------------------------------------------
	;   Irrespective of whether DDRB.PB0 is an Input or Output,
	;     PINB.B0 represents what's going into the USIDR.
	;
	;   To see the contents of the USIDR shifted, you must Single Step on the
	;      command that clocks the USI via USICR.B0
	;
	;   On the next consecutive instruction, for a +ve going SCL (PORTB.B2),
	;      set PINB.PB2 = Logic 1, then Single Step again.
	;
	;      (At this point you're simulating the absence of SCL stretching)
	;
	;   The USIDR contents will have shifted 1 Bit to the left.
	;
	;
	; In real life:
	;   PORTB.PB0 is reconfigured internally as the SDA pin for Input or Output.
	;
	;   With DDRB.PB0 = Logic 1 (SDA Output), PORTB.B0 must be a Logic 1, so as not
	;      to mask the true state of USIDR.B7 that feeds into the SDA pin.
	;          SDA Output pin state = (PORTB.PB0  AND  USIDR.B7)
	;
	;   With DDRB.PB0 = 0 (SDA Input), PORTB.B0 must be either:
	;      Logic 1 (Internal PORTB pullup resistor, NEEDED IN SIMULATION MODE!)
	;
	;   or Logic 0 (No internal PORTB pullup resistor), instead making use of an
	;         external pullup resistor on the SDA pin.
	;
	;   A Logic 0 always wins over a Logic 1 on the I2C SDA and SCL bus lines
	;   because of the wired AND open collector/drain I2C Tx interface.
	;
	;
	; USI Data Collision flag, USISR.USIDC
	;-------------------------------------
	;
	;   Logic expression for USISR.USIDC state = ( USIDR.B7  AND  NOT( SDA pin ) AND  (SCL = 1) )
	;
	;   Only has any significance when the USIDR is Outputing Logic 1 data bits on the SDA bus line.
	;
	;     i.e when outputing 8 data bits as in an Address byte or Data byte,
	;
	;         or during a Acknowledgement clock period, when one I2C device has a Logic 1 on
	;            an input and the other I2C device outputs a Logic 0
	;
	;   Simulation of USISR.USIDC
	;    Using the same Single Step instructions as above:
	;
	;      USIDR.B7     DDRB.PB0     PINB.PB0   =>  USISR.USIDC
	;         1        1 (Output)       1                0
	;         1        1 (Output)       0                1
	;         0        1 (Output)       1                0
	;
	;         1        0 (Input)        1                0
	;         1        0 (Input)        0                1
	;         0        0 (Input)        1                1
I2CTestA:
        nop
	nop
	nop

	sbi   USISR, USISIF              ; Clear USISR flags if status no longer correct
	sbi   USISR, USIOIF              ;   "           "        "                "
	sbi   USISR, USIPF               ;   "           "        "                "
	sbi   USISR, USIDC               ;   "           "        "                "

	ldi   XL, 0x2B                   ; Put PORTB in I2C mode and clock I2C shift register
	out   USICR, XL                  ; toggling between +ve, then -ve clock edges on
                                         ; alternate iterations.

	rjmp  I2CTestA

 

Last Edited: Fri. Dec 29, 2017 - 05:40 AM