SPI programming interfered by other circuitry

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I am populating a custom PC board a section at a time and testing each section before doing the next. I added a couple ICs that connect to SCK and MOSI. After that when I try to upload a test program (with an AVRISP mkII), I get an error saying something about a short circuit. The existing test program runs fine and there isn't any unreasonable current draw.

 

So there is something about the addition of the ICs that the SPI doesn't like while programming.

 

So as a test, I removed the ICs... AVRISP mkII is happy now.

 

QUESTION:

 

Is there some circuitry I should include to help separate the ISP connector from the rest of the circuit?

 

(I'm working on getting a schematic cleaned up - there is a lot of extra stuff that can be removed for clarity)

 

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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Do those other ics actively drive the mosi and sck signals? You might be able to isolate them with 1k resistors. Without a schematic i’m just guessing.

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Thanks Kartman.

 

Your resistor idea is in the realm I was wondering.

 

Here is the schematic:

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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Put pullups on PA0,1 otherwise these will float whilst in reset and cause your observed problem.
According to the data sheet - the 125’s are not needed on SO.

Last Edited: Mon. Dec 11, 2017 - 07:58 AM
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I think both the device datasheets and one of AVR040/AVR042 (can never remember which!) talk about the issues in "sharing" the ISP lines.

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Assuming there are two spare port bits, you could get rid of two ics and avoid the problem altogether.

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Kartman wrote:
Put pullups on PA0,1

I'd have to follow through with the datasheets for all of the attached devices.  But I will [strongly] recommend you re-word your advice:

 

"Connect weak pullups or pulldowns to the select signals of attached SPI devices, in a direction to keep the SPI device de-selected when the AVR is in reset and not driving the signal."

 

If you do that, IME, you do not need serial isolation for ISP signal integrity purposes.  (If you want it for e.g. external static protection that is up to you.)  IME serial isolation may be needed if there is no choice but to have interfering app circuitry on one or more of the ISP signal pins.  IME can usually be avoided on larger pin-count models.  But e.g. Tiny85 app with limited pin allocation choices -- in a couple apps, we have to mount components after ISP.

 

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Kartman wrote:
Put pullups on PA0,1 otherwise these will float whilst in reset and cause your observed problem.
According to the data sheet - the 125’s are not needed on SO.

Thanks Kartman. This is quite helpful. I had suspected the 125s may be unnecessary.

Kartman wrote:
Assuming there are two spare port bits, you could get rid of two ics and avoid the problem altogether.

This is also helpful. When originally designed, there were no spare port bits, but that may have changed....

theusch wrote:
Connect weak pullups or pulldowns to the select signals of attached SPI devices, in a direction to keep the SPI device de-selected when the AVR is in reset and not driving the signal.

Thanks theusch. In this case, it appears the pullups on both will satisfy your advise (and it's helpfull to know why). Also, "weak" is important to note.

 

Cris

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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aeroHAWK wrote:
(and it's helpfull to know why).

You mean because some SPI devices use active-high CS and others use active-low /EN?  And it is not unusual to have them on the same system/SPI bus.

 

aeroHAWK wrote:
Also, "weak" is important to note.

Doesn't it make sense that you do not want them so strong that the AVR driving circuitry has to fight the signal?  And how much current does it take to bias a truly floating signal, such as the chip-select lines when the AVR is in reset and they are floating?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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So there is something about the addition of the ICs that the SPI doesn't like

 I probably need more sleep...

 

Medicine is easy, by the way, compared to electronics.

Red blood is flowing away from the heart.

Blue blood is flowing towards the heart.

Or something like that.

 

Anyway, on the Micro isn't MOSI, Master Output, Slave Input, and isn't the micro the Master?

Hence isn't that pin, on the Micro, an Output?

 

It would appear to me that there are two 74HCT125 buffers that are trying to drive the MOSI pin on the micro.

I understand that the multiplexer may only turn on one of these at a time, but doesn't that still leave you with a signal contention, and two pins trying to drive the same line?

 

Finally, why is IRFAN View crashing today?  Windows upgrade broke it?

 

JC

 

 

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In this instance we have a number of spi devices with the /CS actively driven by logic devices. The problem as I see it is that PA0,1 float when the device is in reset - ie ISP mode and thus it is indeterminate what the output of the 139 decoder will be. Pulling PA0,1 high, with say 10k resistors, will ensure output3 of the '139 is active and the other inactive thus disabling the spi slave devices and their intermediate '125 buffers.

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This discussion has been very productive. Kartman's suggestion to eliminate the 125 and the 139 is sound. I have re-allocated port bits and am eliminating those items. I am also able to eliminate other ICs that are not shown on the above schematic. Some I/O that I previously thought needed to be used, has since been found to be unnecessary.

 

I will be modifying the circuit and testing it.

 

Thanks for all the advice.

 

I also forgot to thank Cliff for pointing me to the data sheets.

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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I think U11 can be eliminated also with a little effort. You just need to simulate open drain outputs on the micro side for the chip select pins, by using output low as the low signal and high impedance as the high signal (with pull up to 3.3V). For the SCK signal you can use a diode to block the 5V high, and a pull up to 3.3V.

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As DOC  mentioned, MOSI is an output FROM the micro TO your chips.  Data from your chips goes into MISO  (master INPUT).  A resistor can be used (one is plenty) to separate the chips from the micro/programmer connection, on the MISO line.  SCK & MOSI are outputs from the micro and probably don't need a resistor.

When in the dark remember-the future looks brighter than ever.

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El Tangas wrote:
I think U11 can be eliminated also with a little effort.

Thanks for the suggestion!

 

Since the function of U11 is still required, it is easy just to leave it in place. It is a single device as oposed to several resistors, diodes, etc.  The other ICs were not required at all, so they have been eliminated.

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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avrcandies wrote:
A resistor can be used (one is plenty) to separate the chips from the micro/programmer connection, on the MISO line.  SCK & MOSI are outputs from the micro and probably don't need a resistor.

Thanks - good to know! In this particular example, the MISO line is only connected to the IPS connector. So there is no conflict with that line.

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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 MISO line is only connected to the IPS connector.

WHY? --HOW is the micro going to get data from your chips?  Don't you want the chips to send data to the micro? Remember, PB5/MOutputSI is the micro output pin, PB6/MInputSO the micro input.

When in the dark remember-the future looks brighter than ever.

Last Edited: Tue. Dec 12, 2017 - 02:18 AM
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My suggestion would be to connect the /CS of the three chips together and control this via one pin ( with an external pullup), then bit bash the three chips in parallel - no need to use the spi hardware. Three chips removed, root problem avoided.

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SPI may be fine enough, though just use 2 resistors to divide down the 5V logic to 3.3V CS signals.   Why use the quad decoder, when plenty of free pins to use as CS lines?, or maybe run the quad decoder at 3.3V &  Find one that allows 5V input with 3.3V power (then saves resistors).

 

The chips SO lines can be combined together (assuming only one chip at a time is non-tristate)  & then use ONE gate to convert this combo SO signal up to 5V logic going to the MISO pin

When in the dark remember-the future looks brighter than ever.

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Ahhhh! I didn't spot the level translation requirement or the LVC parts. 

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avrcandies wrote:
HOW is the micro going to get data from your chips?

Okay, so I have my MISO and MOSI reversed!? OOPS! Thanks for the catch.

 

I DON'T have extra I/O. I did free up a few lines but that's all. The schematic above has been edited for clarity that removed excess circuitry that didn't pertain to my original question.

 

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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This is what I have now (the only free I/O pin is PA3, all others are used but not shown here):

 

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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The ISP will probably apply a 5V signal to the SO of the Max devices.
PA0,1,2 will most likely need pullup resistors.

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Assuming you marked things properly, all 3 CSbar lines should be high during programming, so the SO pins will be tri-stat (hi-z) and  not conflicting the programmer. ...to do this, use maybe 10k pullups on PA0, PA1, PA2.

This micro is in reset during programming, so most pins are all floating. 

 

Or it might be better to instead put 5000 ohm resistors in the three individual SO lines...that way the chips are protected against fighting each other (and the programmer).  The fight might be started if you accidentally  turn on more than 1 chip in your code (or during programming).

When in the dark remember-the future looks brighter than ever.

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Kartman wrote:
The ISP will probably apply a 5V signal to the SO of the Max devices.

Yes, I agree. I missed that.

avrcandies wrote:
put 5000 ohm resistors in the three individual SO lines.

As I understand what you are saying, is to add 5k resistors in series on each SO line. That would still allow 5v to the (3.3v) Maxim chip, wouldn't it?

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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What if I do this to address the 5v/3.3v issue on the SO lines:

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

Last Edited: Tue. Dec 12, 2017 - 06:17 AM
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Usingthe hct125 was probably the best solution as it gives you better noise margin. The way you have the resistor divider is not ideal as it decreases the noise margin.

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Kartman had a good catch regarding %V programming signals:

 

Wire all your prog header connections direct to the micro

 

Put an optional 200 ohm resistor on each SO output & tie these 3 resistors together (these prevent direct shorts between the SO outputs).  That's more of a chip safety/software factor than anything.

 

Take the tied connection point & hook 10K to gnd

Take the tied connection point & connect to MISO by 5k series.    ...so you have 5 resistors total (200, 200, 200, 10k, 5k) 

 

When the prog cable is connected it will provide full voltage to the micro pins (assuming programmer can tolerate 5-10k loading, which it should).  The 5K/10k divider prevents more than 3.3v applied to the SO pins from the 5V programmer

 

When the cable is removed, the SO drives the micro pin via 200 +5000 ohms., the 10 k forms a very slight divider (200ohm & 10kto gnd, 98%), giving 3.3V signals at the micro pin.

 

 

Think about possibly running the micro at 3.3V...might be simpler.

 

When in the dark remember-the future looks brighter than ever.

Last Edited: Tue. Dec 12, 2017 - 09:09 AM
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If you are sprinkling resistors about the place just remember that they will form RC filters with any chip IO capacitances, usually low-pass, which means you will mess up your signal's rise times.

'This forum helps those who help themselves.'

 

pragmatic  adjective dealing with things sensibly and realistically in a way that is based on practical rather than theoretical consideration.

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Maybe replace U11 by a level shifter with plenty of channels like http://www.ti.com/product/TXS0108E

One of the channels can be used for the SO/MISO problem.

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Something like a resistor/transistor to form an open collector level shifter. Means you need to invert the data back again in code.
https://www.digikey.com/products/en/discrete-semiconductor-products/transistors-bipolar-bjt-single-pre-biased/292

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Since the PC board already has the HCT125, I am at this point right now:

 

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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no good, when programming, the hct125s will all turn on, short together & drive the miso line

At least put pull ups on pa0/1/2

When in the dark remember-the future looks brighter than ever.

Last Edited: Tue. Dec 12, 2017 - 04:35 PM
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Add pull ups to the /CSx lines,then it should work.

 

Jim

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Add pull ups to the /CSx lines,then it should work.

They need to be on the pa0/1/2 side to work, CS at the chip is being driven 

When in the dark remember-the future looks brighter than ever.

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Thanks guys! This is not as simple as I once thought. After getting the advice, it all makes sense, and it shows me that I make a lot of erroneous assumptions. I'll be adding pullups to PA0, 1, 2.

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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use LVC parts everywhere, the HCT parts cannot accept 5V signals when power by 3.3V, but the LVC can

When in the dark remember-the future looks brighter than ever.

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avrcandies wrote:
HCT parts cannot accept 5V signals when power by 3.3V

Thanks. The PCB layout already powers the HCT parts with 5v and the LVC with 3.3.

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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Just install LVC everywhere & not worry about mix-ups.

When in the dark remember-the future looks brighter than ever.

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avrcandies wrote:
Just install LVC everywhere & not worry about mix-ups.

I thought the LVC part could not handle 5v. So I just checked the data sheet and yes it can! It can handle as much as 6.5v. So yes, I agree, LVC parts everywhere so there are no mix-ups.

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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SOLVED !

 

Thank you to everyone that weighed in on this. Special thanks to Kartman (for warning about the programmer providing 5v to 3.3v devices) and avrcandies (for pointing out that I had MISO and MOSI reversed).

 

The solution is as shown in the most recent schematic with the addition of 10k pullups on PA0, PA1, and PA2.

 

Cris

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)

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DOCJC also pointed out the miso swap, we are all here to help & share our learnings.  Many of us were born with soldering iron fingers.

Good luck on your project!

When in the dark remember-the future looks brighter than ever.

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Oh yes, my apologies to DocJC. I was so overwhelmed by the whole problem I didn't actually understand that he was telling me that (I can have a thick skull). It took a second comment by avrcandies to wake me up. Thanks again to everyone!

 

Cris

Perfection is achieved, not when there is nothing more to add, but when there is nothing left to take away. Antoine de Saint-Exupery (1900 - 1944)