I2C ATtiny85 USI Master USISR USIDC Data Collision

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This topic has a solution.
Last Edited: Tue. Nov 14, 2017 - 06:43 AM
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Either re-type or cut/paste your text, the screen shot is too small/difficult to read!

 

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The Logic Analyser view shows part of a I2C exchange (SCL/SDA) between a single master (ATtiny85) connected to a single slave (DS1307 RTC, I2C module) using the ATtiny85 USI module.

 

The ASYNC trace is showing the contents of the ATtiny85 USISR (Status Register).

For most of the transaction the USISR contents just reflect the 4 bit shift register counter value.

 

I'm not understanding why the USIDC (Data Collision) flag should be set occasionally.

 

      E.g. ASYNC byte 0x016 within the first half of the I2C address byte

 

  USICNT : B0 - B3

  USIDC   : B4    

  USIPF    : B5

  USIOIF  : B6

  USISIF  :  B7

 

What are the intended points within a I2C transaction where the USIDC flag should be used ?

  I understood it to be used in Multimaster situations with respect to SDA arbitration.

 

Is this the correct logic statement for USIDC => (USIDR_B7) and (DDRB_B0) and (/PINB_B0 or /PORTB_B0) ?

 

Thank you.

  Simon

 

 

 

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What exactly is an I2C collision?   I can't find a definition of it on the web except for when there are two I2C devices with the same 7-bit address and both do ACK (assert the SDA line) after the SLA initial transmission.  In the chart it looks like SDA is released and exactly the same time that SCL is asserted.

Last Edited: Mon. Nov 13, 2017 - 12:49 AM
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From the documentation for the ATtiny85, Section 15.5.3 USISR – USI Status Register

 

• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value. The flag is only valid
when two-wire mode is used. This signal is useful when implementing Two-wire bus master arbitration.

 

The I2C exchange shown in the Logic Analyser view completes with no problems.

 

One has to expand the logic analyser view to see that the SDA line transitions only while the SCL is low, typically 40 -150nS after the negative edge of SCL.

This is all under the control of the USI control logic after issuing software instructions to clock the USI shift register.

 

My question is, what causes the Data Collision flag to be set when a single I2C master is connected to only one I2C slave ?

 

Thank you.

   Simon

 

 

 

 

 

 

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My question is, what causes the Data Collision flag to be set when a single I2C master is connected to only one I2C slave ?

Excessive bus capacitance?  Pull-up too weak?

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Further re-reading of NXP Spec, UM10204 I2C Bus Specification and user manual, Rev 6, 4th April 2014 said the following:

 

  Arbitration (Data Collision detection) is done on SDA while SCL is HIGH

     Ref Section 3.1.8 Arbitration

 

So the test code was ammended to show the USISR after generating a positve SCL edge and confirming that SCL had indeed gone HIGH.

 

 

The subsequent logic analyser view, now correctly shows the USIDC flag status on normal Data bits and the Acknowledge bit.