ATMega16 ADC 8 bit mode

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Im using an ATMega16 to detect overload current. So it measures the true rms of the current. I read that the ADC can run at 1 Mhz but with 8 bit resolution. I want to take a reading after every cycle of a 50 Hz signal, so

 

System clock = 8 Mhz, prescaler is 8 so ADC clock is 1 Mhz

Therefore ADC conversion time is = 13 us

So in one 50 Hz cycle there are, 0.02/13*10^-6 = 1538 samples ?  (0.02 is the period)

 

Code:

#include <avr/io.h>
#ifndef F_CPU
#define F_CPU 8000000UL
#endif
#include <avr/interrupt.h>
#include <stdio.h>
#include <util/delay.h>
#include <string.h>

float stepsize = 5.0/256;
float digitalOut = 0;
float rmsCurrent = 0;
float voltage = 0;
float current = 0;
float currentSquared = 0;

int main(void)
{
    while (1)
    {
        adcInit();
        breaker();
    }
    
}

void adcInit()
{
	DDRA = (0<<DDA0);
	ADMUX = (1<<REFS0)|(1<<ADLAR);
	ADCSRA = (1<<ADEN)|(1<<ADPS1)|(1<<ADPS0);
}

void breaker()
{
    for(int i = 0; i<1538; i++)
	{
				ADCSRA |= (1<<ADSC);
				while(ADCSRA & (1<<ADSC))
				{
				}
				
				digitalOut = ADCH;
				
				voltage = digitalOut*stepsize;
				current = (voltage/560.0)*1000.0;
				currentSquared = currentSquared + pow(current,2);
				rmsCurrent = sqrt(currentSquared/1538.0); //True rms
	}
	currentSquared = 0; //Reset after every cycle or 1539 samples
	sprintf(buffer,"%f;",rmsCurrent); //Store in buffer
}

So by setting the ADLAR bit and reading ADCH, will the ADC run in 8 bit mode ?, and then will the step size be 5V/256, where 5V is my reference voltage

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Sgt123 wrote:
So by setting the ADLAR bit and reading ADCH, will the ADC run in 8 bit mode ?,
It always runs in 10 bit mode in fact. ADLAR just makes it easier to pick out the upper 8 of the 10 bits. The point being that because of the successive approximation method it uses first the 10th bit is ready, then the 9th, then the 8th and so on. So if you use ADLAR to get the top 8 bits easily via ADCH it does not matter if the last two bits (now at the top of ADCL) are ready yet as you already have the 8 bits you need "early" in ADCH.

 

And yes, each increment of the ADC you read should be 5V/256 = 0.0195V

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Unless you want to see harmonics from a PWM generated 50Hz, I would say that it's a total overkill to make all those samples, it's more important to have a known (integer) number of samples for each period. 

If this is the only ADC channel you use, and the voltage change between each sample is small, you can expect a better result than 8 bit even with a high ADC clk speed.

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Sgt123 wrote:
Im using an ATMega16 to detect overload current. So it measures the true rms of the current.

Almost funny, IME and in this day and age.  Yeah, one could sample as fast as possible as OP outlined, and calculate the RMS.  Now, if you are spending all of your time gathering and storing and calculation with all of these samples -- when are you going to have time to do the "real" app work?

 

In practice with AVR8s and mains and overload current, even for production commercial devices our hardware designers gave me an external circuit with "RMS Current" being an A/D voltage level.

 

In practice, what kind of device requires fast sampling?  Peak good enough?  Perhaps not if waveform is malformed, but thin I'd think that you'd be bridling at the 8-bit results.

 

Anyway, a decade or two ago "electric meter chips" became available to us punters to do this stuff for only a couple bucks,  feeding off the mass-market  for energy meters.  e.g. Analog Devices ADE7xxx series.  Far more sophisticated than any of us could do "by hand".

 

(And why a Mega16 in 2017?!?)

 

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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So if you use ADLAR to get the top 8 bits easily via ADCH it does not matter if the last two bits (now at the top of ADCL) are ready yet as you already have the 8 bits you need "early" in ADCH

I don't think that's so.  That is, I don't think the bits are populated in ADCH/L 'as they come in'.  Instead, they are tabulated internal to the ADC logic and then latched to ADCH/L I/O register pair in the last rising edge of the ADC clock during a conversion, at the same time that ADIF is set.  Prior to that, ADCH/L will contain the results of the previous conversion, or 0x000 if no previous conversion has taken place.

 

 

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"Good judgement comes from experience.  Experience comes from bad judgement."

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clawson wrote:
it does not matter if the last two bits (now at the top of ADCL) are ready yet as you already have the 8 bits you need "early" in ADCH.

Cliff,

Are you saying that if one keeps reading the ADCH register the upper 8 will be available BEFORE the AD Complete flag sets? 

 

JIm

If you want a career with a known path - become an undertaker. Dead people don't sue! - Kartman

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB user

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jgmdesign wrote:

clawson wrote:
it does not matter if the last two bits (now at the top of ADCL) are ready yet as you already have the 8 bits you need "early" in ADCH.

Cliff,

Are you saying that if one keeps reading the ADCH register the upper 8 will be available BEFORE the AD Complete flag sets? 

 

JIm

I do not think so as per joey's explanation. but it might be an interesting experiment the OP can do

write an assembly program that starts ADC and then fills R0 through R31 with adc results and the adc status register that would be 16 reads, but as a conversion should be finished in 13 I think you max will be able to do 5 or 6

 

additionally the OP uses floats. small tip is to use integers instead, will safe a lot of code space and computational time. and hopefully he has included all the float libs and parameters in studio to actually make floating point calculations possible. It has been years since I have used them last, so might be that in AS7 they are ON when teh compiler sees a float definition, but my best guess is that you have to manually adjust a couple of project settings to actually make floats work.

 

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This passage from the datasheet is not definitive:

 

 

...  but I believe it support the notion that ADCH/L is latched.  That is, imagine that a conversion is under way when you read ADCL.  Until you read ADCH, access to ADCH/L by the ADC logic is disabled.  The warning above is w.r.t. what will happen if that access is still disabled at the moment the ongoing conversion completes.  Were ADCH/L populated with bits from the ADC logic 'on-the-fly', I would expect the warning to be "don't attempt to read ADCH/L during a conversion >>at all<<", rather than "make sure you've re-enabled access to ADCH/L by the ADC (by reading ADCL) before a conversion completes".

 

I don't recall ever explicitly testing this in my experiments with the ADC.  If I have time later I'll whip something up, but I'm not likely to be near my shop for at least a few days, and I have no gear with me here at home this week.

 

In any event, this whole discussion is really a bit of an OT...

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"Read a lot.  Write a lot."

"We see a lot of arses on handlebars around here." - [J Ekdahl]