I2C bit sequencing, eeprom write

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Hi, Im looking at code that is directly setting the bits for SCL and SDA, with appropriate delays. Aiming to get code for a eeprom write read from an M8.

 

Well there are "tutorials", "specifications" (especially for the one chip Im working; 24LC16), "all you need to know" etc.

 

However, all more or less contain exactly the same text with minor variations and same figures. None of which I can find

to describe the sequence for receiving the ack after a byte write, when multiple bytes are written.

I.e. Im currently into trying to get the sequence for write to eep right. (possibly I have an eye problem, or dont read well enough)

(There can also be different take in same document; where the SDA (from the acking part) goes high IN the SCL flank or in the following SCL low (doubious) )

 

Well, would appreciate if someone has a pointer to good description, or can explain the order, and where the next byte starts after the ack reception. (like some german text

... :) )

 

/g

Last Edited: Sat. Oct 7, 2017 - 08:44 PM
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I suggest that you use the TWI section of the Mega8 to interface with I2C.  Directly setting and clearing the bits to do I2C has to be done exactly with microsecond precision.  

 

Basically to interface to an EEPROM,  start with both SDA and SCL unasserted (released, logic high).  Assert the SDA, wait a few microseconds, assert the SCL.  Now assert or release the SDA for the most-significant bit first, and release the SCL.  Wait a few microseconds, and re-assert the SCL.  After the eight bits, change the SDA to an input and release the SCL.  Check that the SDA is asserted: this is the ACK bit.  The slave will assert the SDA during the ACK interval.

 

This is done for each byte: 8 bits MSB first, followed by a ACK bit.  

 

The first byte of the sequence will have a Slave address in bits 7-1 and the read/write bit in bit 0.

 

Let me say again that it would be best to use the TWI section of the Mega8 to interface with I2C.  It is complicated, but it works well and the CPU handles all the timing.

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Ok, I think I hear you. Possibly that could be good way out. Didnt seem too much trouble to bit-bang the functionality though, at first sight. Doesnt seem that tolerances on timing

are all that great. Well PC5 I actually have kept free, and PC4 might just be possible to use in alternate PIN use. However; the blob in the M8 ref. man for TWI is HUGE. Seem

to be more work penetrating that then writing own, not needing the "bus" features, just p-p eep.  Cant understand that I have missed it, guess I have megajumpted the chapter :)

thanks. Your basic description I do follow (and have a rough implement that do). However I havnt tested it. The common figures explaining the protocol, have a little SDA spike after the 

read of ack, in the output-byte sequence, is that the ddr shifting back to output from input (wth pullup) ? and why is the spike going low. And does the SCL just tick on in the same pace when the next byte is following, and the first bit then in the very next SCL-high after the ack-read ?

 

Anyways, Ill check the built in TWI support. (also my use of the eeprom is not time/processor critical, no need to offload CPU).  (isit Botticelli ?)

 

/g

Last Edited: Sat. Oct 7, 2017 - 09:34 PM
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For I2C, we all use Peter's code, http://homepage.hispeed.ch/peter...

it has demo code for talking to an eeprom, and has both TWI code and bit bang code.

 

Hope that helps

 

Jim

 

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I2C is most complex IC-to-IC interface used in computer CPU systems.  Interfaces like SATA and USB are more complex, but these connect stand-alone computer systems.  I2C is designed to connect up to 126 individual ICs to the microprocessor with only three shared wires: SDA, SCL, and ground.  Think of logic high (+3.3 or +5V) as the released state and logic low as the asserted state.  Both SDA and SCL will be at released state when the I2C is not in operation.  Basically they are inputs that are pulled high by external resistors in the released state and are outputs that are pulled low in the asserted state.  Try downloading all the I2C tutorials that you can find on the web and understanding how they explain the same basic concepts with different wordings.

 

Yes, the image is Botticelli's "Venus and Mars" from the National Gallery in London.  This whole "Simonetta" thing started long ago as a joke protest that there were no women in the embedded-systems development industry, so why not pretend to be the reincarnation of Simonetta Vespucci ( the first Italian supermodel who lived from 1453 to 1477) coming back to haunt the 21st century as a microprocessor engineer.  It just continued on through the years.  It's such an unusual handle that I use it on all the web sites that I post on.

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ki0bk wrote:

For I2C, we all use Peter's code, http://homepage.hispeed.ch/peter...

it has demo code for talking to an eeprom, and has both TWI code and bit bang code.

 

Hope that helps

 

Jim

 

 

+1

 

Another Jim

If you want a career with a known path - become an undertaker. Dead people don't sue! - Kartman

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB user

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Ok, thanks both. And having started look at M8 Ref man I think some pieces will come there (that refman is quite good clear language).

Interresting with Simonetta . Well guess there still arnt many ladies out there reading manuals all night :)

 

(( And having read some further in the M8 ref (in connection with fig 73), I think answers my Q above: the SCL can be pulled low by the counterpart, in order to

give the counterpart (slave, in my case the eep) more time to process the received data (byte), if the speed of master clock (SCL) is too high. Might though not be

needed to check for that low-pulling if speed is kept low, I have no time issues))

 

/g

Last Edited: Sun. Oct 8, 2017 - 09:46 AM
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Hi again. Well looking at P Fleury's, I think I stop thinking and compile&use his twimaster.

tnx again

/g

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Simonetta wrote:
I2C is most complex IC-to-IC interface used in computer CPU systems.
Usual BS. So it's more complex than Ethernet for example? 

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What's new?
You can always rely on Simonetta to express an opinion.

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Somewhat reassuring, possibly Ill try my hack sometime after all..... :)

(and yes, I wouldnt try to do Ethernet, at least not from phy level )

 

/g

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For clarity, SATA, Ethernet, PCI, USART, etc... are interfaces between two systems with each one being microprocessor-based.  I2C and SPI connect the ICs internally on a single microprocessor-based system.  So, indeed, SATA, Ethernet, PCI are going to be more complex than I2C and SPI.  But I2C is the most complex interface that you will find that connects the ICs inside a single microprocessor-based system.

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Two micros can (and often are) connected by Ethernet but if you want a real world example of micro to micro connection that is substantially more complex than I2C try CAN. Many models of AVR have CAN peripherals.  Programming them makes I2C look like a trivial walk in the park! 

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ki0bk wrote:
For I2C, we all use Peter's code, http://homepage.hispeed.ch/peter... it has demo code for talking to an eeprom, and has both TWI code and bit bang code.  

 

However I seem to miss out on the twi.h file in the i2cmaster.zip .... anyone has a clue ?

Last Edited: Sun. Oct 8, 2017 - 06:46 PM
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TWI.h is part of the GCC toolchain....it's in Studio

 

JIm

If you want a career with a known path - become an undertaker. Dead people don't sue! - Kartman

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB user

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Ok, thanks, I had that thought, and was looking for the avt-gcc installation, I have switched machines and had that installed by own rights before,now I have installed the atmel studio, and havnt found the atmega definition .h files anywhere.

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YOu do not need to look for them.  simply INCLUDE them at teh top of your code

 

#include <util/twi.h>

Jim

 

If you want a career with a known path - become an undertaker. Dead people don't sue! - Kartman

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB user

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HEY !!

 

just a minor detail I just discovered, not tested yet:  there are 24LC16....... yes or more specifically 24LC16A  and 24LC16B, ... the specs for them are just ...nearly... identical,

but for one thing, the addressing for A is done by two bytes, while the B variant is addressed by 1 byte. Ive been using the A spec downloaded, while having bought the B variant, ...

(until I now was on another computer, now without my work directory thus downloading the spec, anew, I thought, but hey...)

As one dear, now no longer present, colleague repeatedly insisted; the devil is in the details 

 

Well this at least makes for sure that my current code won't work, lets hope...... (intermittant coder as I tend to be )

Last Edited: Tue. Nov 7, 2017 - 11:46 PM
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I don't believe you.   Please post a link to a 24LC16A datasheet.

 

Surely all 24xx16 variants all use 1-byte CONTROL-BYTE and 1-byte WORD-ADDRESS as shown in 24LC16B data sheet.

The upper 3-bits of the location are encoded in the CONTROL-BYTE.   the hardware A0, A1, A2 pins do nothing.

 

You can expand 24C02, 24C04, 24C08 memory array with the hardware address pins e.g. up to the 2048 bytes of a single 24C16.

 

The larger EEPROMs like 24C32 to 24C512 use 2-byte WORD-ADDRESS.   You can expand the memory array with the hardware address pins e.g. up to the 65536 bytes of a single 24C512

 

David.

 

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Sorry; reading your post again, Im too quick and reading wrong. So we do agree on the 24LC16B not having the possibility for multiple chips on bus.

So the spec I have wrongly taken must have been one of the C variants..... check in a moment (other computer)

SO anyways, I entered this post to warn that there are very similar specs; and yes you are very right, the A i have shuffled around (in my sloppy brain),

the full spec is FM24C32A,  that I previously downloaded. (kind of dyslexia ? =)

 

So it can still be the reason why my 24LC16B chip is not responding as I percieve it should.

 

http://ww1.microchip.com/downloa...

 

Is the link Im refering to as my "newly" found link, and here the 24LC16B is NOT possible to have in set of several on the buss,giving address A0,A1,A2 pins.

But the space for that in the first byte/control is used for block pointing instead, and thus removing one byte in the communications. 

 

thanks for help, and hold a thumb that my code now works proper

 

Last Edited: Wed. Nov 8, 2017 - 08:57 PM
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Well now my bit-bang code works for write&read byte operations.

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As a followup question someone might have some think on:

 

I am short of pins for my project, which is one of the reasons I developed the bit-ban mem com, anyways, my question is:

Do you know how the chip reacts if SCL goes up and down while SDA is high..... (and this being outside start-stop, ie when the line is supposed to be idle)

of cause I could experiment, but then I still could not be really sure what the chip thinks.  (this way I could use my LED heartbeat PIN for my infrequent memory accesses)

 

 

/georg

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An I2C device will ignore SCL if SDA remains high.

 

Your EEPROM datasheet shows the Start, Stop, Valid Data timing diagrams.

 

An I2C device will respond to Start, Stop.   It will only respond to Valid Data after it has received a valid Start + Address.

 

David.

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OK, thanks a lot, as I would have thought,and wished. So my heart-beat will get som arythmetics :)

 

/georg