SAMD11 48DFLL Accuracy

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I mentioned in another thread that I began by using the ASF USB UART project as a basis for my project but then ran out of ram when adding my own code so I began migrating to a non-ASF code base.  In this process I'm noticing that my DFLL clock accuracy seems to be different.  At first it was really noticeable but now it seems to drift in and out of  48MHz.  Last night I wrote some code to use TC1 clocked from the DFLL to measure a 60pps reference every 15 seconds for 3 hours, this was the result:

And the Histogram:

I went back and ran both programs to compare the DFLL Registers, this was the result:

So I do notice that the FSTEP and CSTEP registers are different, I've made that change and need to re-test but I'm still curious if there is a better strategy for using DFLL.  This board does not have the capability of using an external xtal.  Right now it is USB connected but it would be ideal to have something that works without USB too.  In general I am curious if something like the internal OSC32 can be used as a reference and if that improves things?  When I try to set that up, the chip just goes into reset :(

BTW, here is my current clock code:

	uint32_t coarse, fine;

	SYSCTRL->OSC8M.bit.PRESC = 0;

	SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
	SYSCTRL_INTFLAG_DFLLRDY;

	NVMCTRL->CTRLB.bit.RWS = 2;

	coarse = NVM_READ_CAL(DFLL48M_COARSE_CAL);
	fine = NVM_READ_CAL(DFLL48M_FINE_CAL);

	SYSCTRL->DFLLCTRL.reg = 0; // See Errata 9905
	while (0 == (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY));

	SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_MUL(48000);
	SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE(coarse) | SYSCTRL_DFLLVAL_FINE(fine);

	SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE | SYSCTRL_DFLLCTRL_USBCRM | SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_CCDIS;

	while (0 == (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY));

	GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(0) | GCLK_GENCTRL_SRC(GCLK_SOURCE_DFLL48M) |
	GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN;
	while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);

I really appreciate the 2nd set of eyes that this forum offers!

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Ok here is a quick update.  I re-ran the test again with CSTEP = 1 and FSTEP=1.  The results are much better now.  I don't know if I just got lucky or the issue will pop up again, only time will tell.  I'm still curious what the best 48DFLL scheme would be for a device without XTAL and with optional USB.

And the Histogram:

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I found out much the same with a Sparkfun SAMD21 breakout board , see https://community.atmel.com/foru... Here I used the PPS from a GPS module and measured the number of counter cycles in each second. 

It was possible to use an external 4MHz quarz attached to two breakout pins, A 1MHz timer clock derived from the quarz showed a variation of +-1 count/second

I suggested to Sparkfun some time ago that they should make it possible to use an external quarz on the board, but they said that there were no plans for changing it. There's certainly space for a quarz and two capacitors

Jerry