ASF configuration for the custom board

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In most of the ASF drivers; board, clock, and oscillator are very important. So, how should I config those settings if I use a custom board, XTAL1, 16MHz oscillator? The 'sysclk.h', 'BOARD_OSC0_HZ' and 'oscctrl' always confuse me a lot.

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What I use is Crystal 1 not 0. However, there is the only BOARD_OSC0_HZ. Is it the same that I fill the value of OSC1 into the OSC0.

And the most important problem is...

Severity Code Description Project File Line

Error 'BOARD_OSC0_HZ' undeclared (first use in this function) GccApplication1 C:\Users\Frank\Documents\Atmel Studio\7.0\GccApplication1\GccApplication1\src\ASF\common\services\clock\uc3b0_b1\pll.h 257

I have tried to define that in the source file or macro file but it was no use.

What should I do to solve this?

NOTE:

I find a line 

#ifdef !defined(BOARD_OSC_HZ)

#define BOARD_OSC0_HZ UNDEFINED

......

But it has been defined in the same and the other macro files, how can it is not declared?

 

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What is in your conf_clock.h file ?

Last Edited: Sat. Sep 2, 2017 - 07:32 AM
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/**
 * \file
 *
 * \brief Chip-specific system clock manager configuration
 *
 * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
 *
 * \asf_license_start
 *
 * \page License
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * 3. The name of Atmel may not be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * 4. This software may only be redistributed and used in connection with an
 *    Atmel microcontroller product.
 *
 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * \asf_license_stop
 *
 */
/*
 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
 */
#ifndef CONF_CLOCK_H_INCLUDED
#define CONF_CLOCK_H_INCLUDED

//#define CONFIG_SYSCLK_INIT_CPUMASK  (1 << SYSCLK_SYSTIMER)
//#define CONFIG_SYSCLK_INIT_PBAMASK  (1 << SYSCLK_USART0)
//#define CONFIG_SYSCLK_INIT_PBBMASK  (1 << SYSCLK_HMATRIX)
//#define CONFIG_SYSCLK_INIT_HSBMASK  (1 << SYSCLK_MDMA_HSB)

#define CONFIG_SYSCLK_SOURCE          SYSCLK_SRC_RCSYS
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_OSC0
//#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLL0

/* Fbus = Fsys / (2 ^ BUS_div) */
#define CONFIG_SYSCLK_CPU_DIV         0
#define CONFIG_SYSCLK_PBA_DIV         0
#define CONFIG_SYSCLK_PBB_DIV         0

//#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_OSC0
//#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_PLL0
#define CONFIG_USBCLK_SOURCE          USBCLK_SRC_PLL1

/* Fusb = Fsys / USB_div */
#define CONFIG_USBCLK_DIV             1 /* Fusb = Fsys/(2 ^ USB_div) */

//#define CONFIG_PLL0_SOURCE          PLL_SRC_OSC0
//#define CONFIG_PLL0_SOURCE          PLL_SRC_OSC1

/* Fpll0 = (Fclk * PLL_mul) / PLL_div */
//#define CONFIG_PLL0_MUL             (48000000UL / BOARD_OSC0_HZ)
//#define CONFIG_PLL0_DIV             1

//#define   CONFIG_PLL1_SOURCE          PLL_SRC_OSC0
#define CONFIG_PLL1_SOURCE          PLL_SRC_OSC1

/* Fpll1 = (Fclk * PLL_mul) / PLL_div */
#define CONFIG_PLL1_MUL               (48000000UL / BOARD_OSC0_HZ)
#define CONFIG_PLL1_DIV               1

#endif /* CONF_CLOCK_H_INCLUDED */

I have modified a bit.

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MrAn wrote:
What I use is Crystal 1 not 0. However, there is the only BOARD_OSC0_HZ. 

So make an equivalent BOARD_OSC1_HZ, taking the existing BOARD_OSC0_HZ as your model.

 

In fact, it would seem more sensible to have a BOARD_OSC_HZ which is set to either BOARD_OSC1_HZ or BOARD_OSC0_HZ at the user's selection; eg

#if defined USE_USC0

#define BOARD_OSC_HZ BOARD_OSC0_HZ

#elif defined USE_USC01
#define BOARD_OSC_HZ BOARD_OSC1_HZ

#else
#error "must define either USE_USC0
 or USE_USC01"
#endif

Then the rest of the code just uses BOARD_OSC_HZ ...

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Uhmm.. It makes sense. However, when I defined the BOARD_OSC1_HZ instead of BOARD_OSC0_HZ, output reports an error 'BOARD_OSC0_HZ not declared'. What really surprised me is that the program still worked when I defined BOARD_OSC0_HZ even if I use XTAL1. And sysclk_init() is seemed not necessary for the program still worked even if it is commented.......

It seems that ASF may not as difficult as I think. However, I have to say that the header files contain a lot of probabilities, which makes the code hard to understand neatly.

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Post #3 : "Error 'BOARD_OSC0_HZ' undeclared ..."
occurs because CONFIG_PLL1_MUL is undefined because your conf_clock.h has #define CONFIG_PLL1_MUL (48000000UL / BOARD_OSC0_HZ)
You want to use OSC1 so you (reasonably) did not define BOARD_OSC0_HZ
Change that #define to #define CONFIG_PLL1_MUL (48000000UL / BOARD_OSC1_HZ)'
The question now is, why did the autogenerated conf_clock.h use OSC0 for CONFIG_PLL1_MUL ?
My guess is because most people would use OSC0 even though PLL1 can be driven from OSC0 or OSC1.


If you do not use sysclk_init() (or do your own clock startup/selection) then the processor will use the default power-up/reset internal 115 kHz RC clock.

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For some modules that are seemed to use the time base don't have the conf_clock.h, which means that there is no selection of oscillator. For example, if I import 'PWM', there is no conf_clock.h imported but it has the period setting and 'diva' or 'divb' is inside the header file. 

For some other MCUs such as ATMega, they have the fuse bit settings for master clock selection. So for UC3B, is there any fuse bit setting for selection of clock? Or the master clock is already set to internal RC oscillator?

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MrAn wrote:
when I defined the BOARD_OSC1_HZ instead of BOARD_OSC0_HZ, output reports an error 'BOARD_OSC0_HZ not declared'

Well, obviously that is bound to happen - isn't it?!

 

When you change the definition, you obviously also have to change the references to match!

 

Which is why I suggested having a generic BOARD_OSC_HZ which is selected as either BOARD_OSC1_HZ or BOARD_OSC0_HZ

 

 

What really surprised me is that the program still worked when I defined BOARD_OSC0_HZ even if I use XTAL1.

That doesn't seem surprising at all: clearly, BOARD_OSC0_HZ is just being used to indicates the frequency - not to define the source.

 

 

And sysclk_init() is seemed not necessary for the program still worked even if it is commented.......

Then, presumably, you happen to have hit a set of defaults that happen to work at the moment.

 

 

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Yeah, you are right. And even for some modules that don't have sysclk def, I have to import it. The PWM timebase seems so long that the LED connected to a PWM pin blinks instead of dim...

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The clocks are configured in the PM (Power Manager) module, (and depending on the processor, the SCIF).
At first glance it looks very complicated and there are many options, but it basically consists of ;
Enabling a clock source, waiting until it is ready and then selecting it as the main system clock.


The UC3Bxxx cannot use OSC1 as the main system clock, but it can use PLL0, and PLL0 can use OSC1.
Things get a bit complicated if you use the PLL because there are frequency constraints that need to be met.

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mikech wrote:
The UC3Bxxx cannot use OSC1 as the main system clock

That would explain why they don't have a #define for it, then!!