SAMD21 hardfault on setting CC2 register on TCC1

Go To Last Post
3 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Hi everyone,

I sometimes get a HardFault on the Cortex M0+ CPU, on lines concerning the setting of the CC register of a TCC:

   while(TCC1->SYNCBUSY.reg  & TCC_SYNCBUSY_CC2) { }
   TCC1->CC[2].bit.CC = TCC_MASK & (_pps_capture + PROCESSING_DELAY); // <- here

Any idea what causes this? Thanks!

Regards,
Vincent

 

 

This topic has a solution.
Last Edited: Fri. Sep 1, 2017 - 06:27 AM
This reply has been marked as the solution. 
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

The SAMD21 TCC1 only has two CC registers, while TCC0 has four. This may explain the fault

Jerry

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Ah yes, that would do it. Funny I didn't see this in the documentation... Anyway, thanks for your help!

Regards,
Vincent