TWI master read stuck using XDMAC

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I'm trying to implement I2C master using the XDMAC controller of the SAME70.

My TWI DMA software implementation is based on the E70 manual chapter  42.6.3.9 Using the DMA Controller (DMAC) in Master Mode.

So far I succeeded in implementing TWI master read/write with polling and master write using XDMAC but failed on master read using XDMAC.

 

On the scope I can see that the first byte transferred on I2C seems to be fine but the second byte read is stuck after the 7th clock cycle. Looks like the DMA hardware hung up and the question is how this can happen.

The master ties the clock low forever until if I restart the master. Then the clock goes high again. No XDMAC interrupt is generated if the read hangs up although all XDMAC interrupt bits including bus errors are activated.

 

The following screen shots show the first byte receive timing and the second shows the incomplete second byte. Any ideas ?

 

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SAME newbie

Last Edited: Thu. Aug 31, 2017 - 05:45 PM
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Hi,

 

Some code would be helpful. However, from your scope images I notice two things.

1) Is the blue channel the data channel? If so, why is the data channel being pulled down all the time? What is the small increased level at the 9th clock in the first image? If its an ACK, its not very convincing.

2) I see that during transmission the clock channel is also not pulled down completely. Maybe the resistor value is too low? It seems like the MCU can't drive the bus correctly.

 

Regards,
Vincent

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Finally I found a mistake in my code and now the RX DMA works as expected. After copy/paste I forgot to change the DMA address from THR to RHR TWI register. So the DMA was reading from the transmit register by mistake...

 

Vincent: I checked the signals on the I2C bus and in my understanding this behaviour is related to the I2C bus driver/repeater. Please let me know if you do not agree.

In my application the I2C master has an PCA9515A chip onboard. The SCL and SDA signals have 10kohm PU resistors connected to 5V as shown in the screenshot below.

An SAME70 XPLD board acts as I2C slave, the I2C signals are connected to the GPIO pins of the E70 MCU.

 

Regarding the PCA9515A datasheet the master's low is typically 500mV. The slave can drive low below 500mV. Therefore there are two different low levels on the I2C bus.

 

Here the relevant part of the data sheet as screenshot:

 

 

 

SAME newbie