ADS8332 Interfacing With MCU

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Hi,

 

I have a question about how I can go about polling or using interrupts for ADC values on an ADS8332.

It's a 16-bit, external ADC that I have connected via SPI on my XmegaA3.

 

The context is that so far I can read back the device's Configuration Register (CFR). The ADS has two registers, a Command Register (CMR) that takes up bits 15:12, and the CFR register which takes up bits 11:0. So the good thing is that the SPI is working, and seems to be set-up okay to communicate with the ADC.

 

The problem is when I try reading the values. At the moment, I have a Read Value function that plain and simple doesn't work. I get back weird clusters of 1's like 0xff, 0xfe, or 0xfb. Like I said, it's wrong, but here it is, where the first command 0xd0 writes a Read request to the CMR. It's 3 bytes of data because the last byte is meant to hold the tag bits that tell what channel it's from.

/*********************************
ADS8332 Read Data
**********************************/

void Read_24Bit_Data(uint8_t *Data) {

	PORTC.OUTCLR = PIN4_bm;			_delay_ms(2);
	Data[0] = SPI_Data_Transfer(0xd0);	_delay_ms(2);
	Data[1] = SPI_Data_Transfer(0x00);	_delay_ms(2);
	Data[2] = SPI_Data_Transfer(0x00);	_delay_ms(2);
	PORTC.OUTSET = PIN4_bm;
}

I call this function from a while(1) loop in main. TI's forum suggested that I use the Eval. Board's interrupt pin to indicate an end-of-conversion (EOC) and that's what I'm asking help for. I'm wondering what the pseudo-code for that might be. I'm thinking that I will

 

1. Setup an ISR with a generic pin change interrupt trigger, with the pin connected to the board's interrupt pin

2. Clear the interrupt pin inside the ISR

3. Call the Read_Data function inside the ISR

4. Return to main

They say in the datasheet that

This status pin can also be used as an interrupt output, INT (CFR_D[7:6] = 10), which is set low at the end of a conversion, and is brought high (cleared) by the next read cycle. The polarity of this pin, whether used as EOC or INT, is programmable through the CFR_D7 bit.

 

This is a picture of the timing diagram, and this is the datasheet.

Does this look like a good plan? Thanks

Last Edited: Wed. Aug 16, 2017 - 01:41 AM
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How fast do you want to sample? 500ksps is a sample every 64 clk cycles, so an isr is going to chew up most of them.

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Ok true, thanks for the heads up. I got the ADC to work, so damn am I glad. 

I think I'll try it with DMA