ATAES132A Basic Encryption/Decryption

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Hi Everyone,

 

In ATAES132A datasheet on pages 112, 113 and 114 we have described process of Mac generation, Encryption and Decryption. 

In this explanation there are used two modes of encryption/decryption - CBC and CTR.

I'm facing ATAES132A with uC using my own AES C library. Now after Auth Command(Outbound Only Authentication) or EncRead I would like to retrieve data on uC. To do this things I need a couple of input's which I don't know how to get, starting from the end (decryption):

  • A counter block (Initialization Vector for CTR).
  • A nonce computer by chip (one way to know the nonce I think is to provide it by Nonce command from the uC).
  • A Initilization vector for CBC mode for decryption.

Also I don't know how is constructed Counter Block for CTR - how many bytes are used by Nonce and how many bytes are used for counter.

I was reading many times specifications of AES, modes of operation and CCM specification but I have know idea how to connect all these informations with ATAES132A.

I know I missing something simple, but I don't know what is this.

I'm counting for any help or hint.

Thanks in advance, Daniel.

 

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I created the attached spreadsheet while writing a library for this chip and found I almost always had it open to refer to.

It shows all inputs for all cryptographic operations, configuration register settings and counter operation.

 

All the information you need is in either the ATMEL datasheet or the NIST CCM specs:

 

http://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-38c.pdf

 

Enjoy.

 

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Last Edited: Wed. Aug 9, 2017 - 01:50 PM
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Wow, 

 

anha6317 thank You very much for sharing your work, I have to wait until monday to check this with ACES and add some functions to my library, I will post some basic example after success. The one good information is that (I think from the excel) I can compute Nonce via my library. Also now I know IV for CBC and how is constructed Counter block for CTR. Correct me if I'm wrong, is counter occupying last two bytes in this block? 

 

Thank you very much for that one more time, I was running around without these informations, also I have readed couple of times CCM Standard but it's too much abstract. Atmel should give one example of these calculations. 

 

I hope You will have a nice weekend, Daniel.

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Hello anha6317,

 

I have one more question if I may, In your spreadsheet, on Nonce sheet is described Nonce computation.

When you making these computations on uC, how do you know 'RNG seed' value in Block A?

 

 

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1) Yes - in a CTR block the counter value is the last two bytes of the block. CTR_0 is used to encrypt the MAC. CTR_1 and CTR_2 are used to encrypt the plaintext blocks.

 

2) The RNG seed value is your decision. You can use the rand() function of whatever language you are using. I use bit 0 from a free running ADC to build the seed.

 

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ad 2). Yes, and after computing Nonce in that manner you are sending it to ATAES132A by Nonce command in Inbound Nonce Mode. 

I mean there's no way to read ATAES132A RNG seed?

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Not quite. I always use a Random Nonce in my code and I force the keys to use a random nonce.

So to synchronise my nonce with the chip......

 

1) Generate a 12 byte seed value

2) Send this seed to the chip with the Nonce command, where mode byte bit 0 = 1

3) Using the method in the excel spreadsheet, use the random number (RNG) returned by the chip to calculate the new nonce.

 

There is no way to read the chip's current seed value.

 

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Yes, yes, yes,

that's correct, everything is working as You wrote. Thank you one more time ;].

 

 

 

 

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Happy to help :)