Laying out an AVR board V2

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This is an update to my previous board here, which I made after implementing the useful suggestions offered in that post and elsewhere online.

In the schematic I have added decoupling capacitors, programming header and a pullup resistor to the RESET pin. I have also removed the loading caps on the RTCs crystal as it was not needed. 

The wire of the label is not being displayed in Eagle (idk whats wrong but no time to figure it out right now). Please take note of the following pins:

PB3 - MOSI
PB4 - MISO
PB5 - SCK
PC6 - RESET

Now onto the board. In the board I have used a ground pour on both sides. I used a simple trace to route VCC to all the required parts, because I was having some difficulty with a VCC polygon. Now I surrounded the crystal with the ground plane as best as I could. The vias around the crystal connect the bottom and top ground planes.

So once again, suggestions are needed. Also I have 2 questions:

1. Can someone please check if I connected the decoupling capacitors correctly in the board.
2. There are three vias that are coming under the TQFN package of the AVR. Now the production house I use does make copper filled vias so the connection will be ensured. I want to ask will it be fine soldering the chip on top.

I am looking forwards to your feedback. Thanks a lot.

PS: Ignore the silkscreen for now, I will clear it up later.

 


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Why start a new thread?

You've als only implemented a small part of the suggestions from the other thread.

For example still no GND / vcc for the LCD. No voltage regulator, layout around the crystals is quite bad Not renaming PC6 to Reset, etc.

 

Also: this does not show much respect to the people who are trying to help.

robo328 wrote:
PS: Ignore the silkscreen for now, I will clear it up later.

 

Cleaning up is a small effort for you and you have to do it anyway.

If you show us a clean post/picture then it is easier for us to spot any remaining errors.

Show us you're trying hard.

 

As a matter of fact I will not answer your 2 questions here (I know the answers) untill you show a bit more effort from your side.

 

@ moderators:

Am I too harsh here?

 

 

 

Paul van der Hoeven.
Bunch of old projects with AVR's:
http://www.hoevendesign.com

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Paulvdh wrote:
Why start a new thread?

+1

 

But as you have, please make a note in the old thread of where the discussion has gone - so people don't waste time making further comments there.

 

EDIT

 

Cliff has done it for you: http://www.avrfreaks.net/comment...

Last Edited: Tue. Jul 25, 2017 - 06:52 PM
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If your board fab shop does plated through holes, I don't know why you are adding unnecessary vias at these locations:

 

      

JP_LCD         and        JP_SPST

 

Comments by previous posters are valid, please acknowledge them...

 

 

David (aka frog_jr)

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Did you use an Autorouter to do the board?

 

JIm

If you want a career with a known path - become an undertaker. Dead people don't sue! - Kartman

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB user

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Don't do a ground fill on top unless you put in a lot of vias to tie it to the bottom. In terms of EMC performance your top fill makes things worse, not better as you've created a whole heap of antennas. Put a fill under the crystal, but use a few gias to tie it to the groundplane.

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Thank you everyone for the suggestions. And I apologize for my behavior. I did not mean any disrespect to any of the wonderful people here. It is just that I want to clean up the silkscreen afterwards because If I clean it up now and find out that I have to do the board again, then it would just be a waste of time. So therefore, I will do it once I know my board is clear of faults.

 Ok so I modified the board to move the decoupling capacitors closer to the pins. But the problem is that now the crystal is a little further away. I don't know if this will cause any problems. Also added a limited GND fill to only two places at the top. Added mounting holes plus a cap for the DS1307.
Suggestions needed.

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For such a simple board there's really no reason for using the autorouter. You can see it does some silly things.
Look at C5 - the fill does nothing. You can wire the cap directly to the pins and a via to the groundplane on the component side.
We've had a couple of similar threads where we've started with a crappy layout and progressed to something production quality. You might want to search them out.

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Kartman wrote:
For such a simple board there's really no reason for using the autorouter. You can see it does some silly things. Look at C5 - the fill does nothing. You can wire the cap directly to the pins and a via to the groundplane on the component side. We've had a couple of similar threads where we've started with a crappy layout and progressed to something production quality. You might want to search them out.

 

I did not use the autorouter. I did it myself. So please blame me for all the mistakes :D.

Anyways, I will sort out that C5. What do you think of the crystal?. Is it not too far from the AVR?

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You could rotate the crystal 90degrees. C1 and 2 can be routed directly to the pins. Why have you chosen such bizarre and torturous paths?
Also, don't run tracks under crystals.- these are sensitive parts of the circuit.
I think you've made some bad design decisions with your supply wiring. Why would you have separate power to the lcd?

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Why would you have separate power to the lcd?

This would be due to the nature of the project as a whole. This board and all other components will be fitted inside a case. The power connector will be outside, so it seemed reasonable to mount the power board at the side and give power to everything from there. 

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You have external power but no protection? Sounds like a recipe for disaster. If there is a possibility for power to be connected backwards, it will happen.
I'd suggest the lcd power comes from the pcb along with the pushbuttons. Also, there's no protection for the switch inputs. You might want to consider this as the real world is rather harsh.

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There is a really odd loop in the back-side trace that goes from JP_SPST and J1, Pin 1. 

 

Personally, I use a different shape pad on pin 1 positions of connectors. J1 is a prime candidate for this.

 

There are traces that join at a very acute angle to the left of C5. Board houses really don't like that and there is no compelling reason for that one. Another to the right of C2 - that one is a bit nasty!

 

The trace arrangement  around the via just below IC1 also has an acute angle though not quite as bad. The layout makes little sense, there. 

 

You have IC1 and U1. Use a consistent reference designator system. If this is EAGLE, you CAN change it. The crystal is marked Q2. Q usually means transistor. X is usually the reference designator prefix for crystals (xtals). Ditto Q1. 

 

You seem to have a trace directly under the pads of crystal Q1. That is a recipe for "strange happenings" with signals being coupled into the clock. Move that trace either right or left.

 

I would argue that the top-side ground polygon on the left does little or nothing. Just drop vias, where necessary, to the ground on the back and be done with it. Only 4 ground vias are really needed and you have 6. The lower one in the middle of U1 does nothing but does not seem to hurt. There is maybe a little more justification for the remaining two and I would probably keep those.

 

At R3, the left pad, the trace can go straight up - it does not have to loop around to the left. 

 

Crystal Q1 (X1?) seems a bit far from the MCU. This is driven largely by size. But, it  still does not thrill me.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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So I removed the redundant traces and simplified the layout a bit. I also removed the top ground pour and cleared up the silkscreen. Also I changed the crystal package to a through hole one. It was smaller and I rotated it to place it close to the MCU.


 

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Still you have strange routing. Try to keep all your tracks on the top layer.
Stop and spend some time thinking of the problem rather than just randomly routing tracks.

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Still you have strange routing.

Are you willing to point it out?

Modified it a little. I do not think that the two jumpers that remain now can be removed.

Last Edited: Wed. Jul 26, 2017 - 01:27 PM
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Kartman wrote:
Stop and spend some time thinking of the problem rather than just randomly routing tracks.

I've suggested to OP to have a look at KiCad and I've even offered to review & edit his schematic / pcb layout.

But OP seems to be so busy randomly routing tracks and he seems completely immersed in his own ideas.

 

On the bright side:

OP has implemented about half of the advise he has been given and the latest change I see is a cleanup of the silk screen.

 

So I'll limit myself here to very small easy to consume tips:

 

To OP:

The number of via's is not really impotant if you are having the pcb manufactured by mail order.

Good ground planes are important. Do not draw long traces through the ground plane.

A plain airplane is flying over the plane. (Correct englisch? (Not native)).

For example The long trace from R3 to J1 (I can read that now) should just dip under the 2 I2C lines and then go back to the top of the PCB.

 

Place C3 and C4 between X1 and IC1

Put the via's for C3 and C4 close to those capacitors.

 

What is the size of your SMD?

Looks like 0603.

0603 is a bit fiddly to solder.

0805 or bigger is (at least for me) easy to work with.

1206 Has the advantage you can more easily read the numbers and you can draw up to 2 traces underneath it.

 

Put Vcc / GND and contrast connections on the LCD connector.

(Ooops, that has already been said (multiple times?)).

Paul van der Hoeven.
Bunch of old projects with AVR's:
http://www.hoevendesign.com

Last Edited: Wed. Jul 26, 2017 - 01:33 PM
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Even more strange routing! And random placement. How thick are your power tracks? Why place the vias so far away from the capacitors? You really don't want the inductance.

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Not pushing, here, just pointing out the benefit of a unique pad shape on connector pin 1. The silkscreen outlines that you have are generally sufficient for component placement. But, what happens when you need to debug with a meter or logic analyzer or scope on the back side of the board. THEN, it is really hard to tell which is which. That is how I have learned, over the years, to put something that I can identify from the both the front and back side. Pad shape is an easy way to do that.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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(Although probably not critical in this design,) the GND connection on caps C1 & C2 is (relatively) far from the GND pin they are supposed to be bypassing.

Avoid (where possible) multiple traces into SMT pads. They may wick solder from the joint.

(Avoid acute angles into SMT pads.)

 

Quote:
Put the via's for C3 and C4 close to those capacitors.

Why place the vias so far away from the capacitors?

+1

 

Paulvdh wrote:
Do not draw long traces through the ground plane.
+1

 

ka7ehk wrote:
unique pad shape on connector pin 1.
  +1

David (aka frog_jr)