Ok so I have finished laying out a board. I have an ATMega328P running with a 8MHz crystal. The board has two layers and I have chosen the top layer as the ground plane (GND) and the bottom layer as the power plane (VCC). Following design guidelines, I have kept the trace length between the crystal and the AVR minimal. Take a look at the layout and suggest any improvements if you can and also be sure to point out the faults.
EDIT: A lot of people online suggested that I should ditch the VCC plane on the bottom and replace it with a full ground plane with a ground pour also on the top, and both of them connected with vias. Also, I should use a limited VCC pour for all the components that need it. I want to hear your opinion on this point.
EDIT2: Yes I have added the 100nF decoupling capacitors and also the IDC programming header now, which is not in board layout I uploaded because I added them afterwards.