A1U Xplained Pro - Trouble accessing range of SRAM addresses (LPC 2-port)

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Hey y'all,

 

I'm trying to use the EBI (SRAM LPC) feature on my XMEGA A1U Xplained Pro board (relevant datasheets attached).

 

I followed the instructions/guidelines on the AU Manual and EBI AppNote and was able to access addresses 0x4000 to 0xFFFE (approx 50Kilobytes). Given that the SRAM chip used on the Xplained Board has 512KBytes of space, I should be able to access at least 512 or 256Kbytes (based on whether or not I use the A18 pin).

 

Here's the initialization code I've written:

 

PORTJ.DIRCLR = 0xFF;//kk			//Setting all of Port J to Input Mode (data bus) (from AU manual)
PORTH.DIRSET = 0xFF;//kk			//Setting all of Port H to Output Mode (AU manual)
PORTK.DIRSET |= (1<<7);				//Setting K7 to Output Mode

PORTH.OUT = 0xFF;				//"Set signals which are active-low to high value" - http://www.avrfreaks.net/forum/setting-external-sram-project

PORTH.PIN6CTRL |= (0b11<<3);		        //Pulling up H6, because it is the chip-select wire/pin (according to EBI section in AU manual)

EBI.CTRL |= (1<<5);				//SRAM LPC mode: ALE 1 & 2 enabled
EBI.CTRL |= (1<<1)|(1<<0);			//Configure it in 2-port interface mode (according to A1U-XPRO Manual)

EBI.CS2.CTRLA |= (1<<1);			//Set the CS2 to (SRAM)LPC mode
EBI.CS2.CTRLA |= (EBI_CS_ASIZE_512KB_gc);	//Set size of address space to 512kB, because that's how big the external SRAM is.
EBI.CS2.BASEADDR = (0x0);					
EBI.CS2.CTRLB |= (0b111<<0);			//Set longest possible wait length (7 CLK(PER2) cycles per wait state)

Here's what I see on the "Memory" view of Atmel Studio 7 after running the above initialization code. I'm not able to write to the addresses labelled with "??", leading me to believe that those addressed haven't been "activated" (not sure if that's the right word).

 

 

Are there any details regarding either the A1U's EBI feature or the Xplained Board that I haven't taken into account? What can I do to be able to write to the entire (512kByte or 256kByte) address range of the attached external SRAM?

 

Thanks for your time!

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Last Edited: Mon. Jun 12, 2017 - 08:13 PM
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This is an Atmel Studio problem, not a H/W problem.  The XML files that describe the A1U give an external memory range of 0x4000 - 0xFFFF.  If you write a test pattern and read it back, you should find the SRAM is present.

 

 

Greg Muth

Portland, OR, US

Atmel Studio 7.0 on Windows 10

Xplained/Pro/Mini Boards mostly

 

 

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Thanks Greg, I'll give that a shot.

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You should read this thread.

Greg Muth

Portland, OR, US

Atmel Studio 7.0 on Windows 10

Xplained/Pro/Mini Boards mostly

 

 

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AVRGCC can not use the far pointer, addresses exceeding 64 KB can not be specified.
If you want to access the entire memory space, you have to manipulate SFR's RAMPX, RAMPY, RAMPZ, or RAMPD.

As RAMPn affects many addressing operations like bank switching, it should be handled with interrupts disabled.
Refer to the "AVR CPU" section in the data sheet.

As a solution, manage the memory with CS and use arbitrary SRAM address in units of 32 KB of 8000 h - FFFFh.

This will not affect other addressing operations that do not use EBI.

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kabasan wrote:
As a solution, manage the memory with CS and use arbitrary SRAM address in units of 32 KB of 8000 h - FFFFh.
ASF3 has Huge Memory (hugemem.h) to access all of data space.

The equivalent in ASF4 appears to be in-work.

 

http://asf.atmel.com/docs/latest/xmegaau/html/group__hugemem__group.html

ASF4 API Reference Manual

External Bus Driver

http://atmel-studio-doc.s3-website-us-east-1.amazonaws.com/webhelp/GUID-2A8AADED-413E-4021-AF0C-D99E61B8160D-en-US-1/index.html?GUID-507864F6-1424-4D15-879B-AD8CD15937D5

via http://start.atmel.com/ (About)

 

"Dare to be naïve." - Buckminster Fuller

This reply has been marked as the solution. 
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Hey everyone,

 

After a lot of digging and editing, was able to fix the problem.

 

  • BASEADDR needs to be a multiple of the address size (so since I wanted a 256K SRAM address space, the BASEADDR had to be either 0x0, 0x40000, 0x80000, etc.)
  • On the XMEGA A1U Xplained Pro, the SRAM chip has a 512K memory space but the highest bit (A18) needs to be turned on/off manually (using GPIO instead of the EBI module handling it for you). For simplicity sake, I decided not to mess with the A18 pin and instead, just used half of the existing external SRAM space (so 256Kbytes instead of 512Kbytes)
  • If you do set the BASEADDR to 0x0, I found that you will lose the first 0x4000 memory bytes (~49K bytes) because that's where the internal SRAM lives. To get around this, I permanently set my A18 pin high in order to use the other half of the 256K memory block of the 512K SRAM chip (this gives you a nice full 256K of uninterrupted memory)
  • Finally, to read/write all addresses higher than 0xFFFF (highest address that can be represented in 16 bits), I used hugemem pointers and functions from the hugemem.h service from the ASF, as gchapman suggested
    • Note: Importing this directly into my LUFA project gave me a bunch of compiler errors, so I decided to manually copy all the functions, definitions, and includes I needed from the ".h" file itself

 

Hope this helps anyone with similar questions!

 

-by98

Last Edited: Mon. Jun 12, 2017 - 08:14 PM