sysclk_init problem

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Hi,

I'am testing a simple program on XMEGA-A3BU Xplained with ATxmega256A3BU.
The output of the program is 1KHz signal on PORTC,7 = pin 8 on J1.

#include 

#define MYOUT       IOPORT_CREATE_PIN(PORTC,7)
#define OUTFREQ     1000L       // = 1000 Hz

static void ticktimer_callback(void)
{
  static char flag=0;
  flag = !flag;
  if (flag) gpio_set_pin_high (MYOUT);
  else      gpio_set_pin_low (MYOUT);
}

int main (void)
{
  TC0_t * tickTimer = &TCC0;

  board_init();
  cpu_irq_enable();
  pmic_init();
  sysclk_init();
  gpio_configure_pin (MYOUT, IOPORT_DIR_OUTPUT | IOPORT_INIT_LOW);

  tc_enable (tickTimer);  // enable the clock system for the module
  tc_set_overflow_interrupt_callback (tickTimer, ticktimer_callback);
  tc_set_wgm (tickTimer, TC_WG_NORMAL);
  tc_write_period (tickTimer, sysclk_get_per_hz() / (64L*2L*OUTFREQ) - 1);
  tc_set_overflow_interrupt_level (tickTimer, TC_INT_LVL_LO);   // enable interrupt and set low level
  //select the clock source and pre-scale by 64, when the clock source is set, the timer will start counting
  tc_write_clock_source (tickTimer, TC_CLKSEL_DIV64_gc);
  while (1) {};
}

With the original conf_clock.h the output frequency is 1.085 kHz,

#define CONFIG_SYSCLK_SOURCE   SYSCLK_SRC_RC2MHZ
#define CONFIG_SYSCLK_PSADIV   SYSCLK_PSADIV_1
#define CONFIG_SYSCLK_PSBCDIV  SYSCLK_PSBCDIV_1_1
#define CONFIG_USBCLK_SOURCE   USBCLK_SRC_RCOSC

With the Advanced use case - DFLL auto-calibration (XMEGA)
from http://asf.atmel.com/docs/latest...
the output frequency is 1.040kHz

#define CONFIG_SYSCLK_SOURCE                SYSCLK_SRC_RC2MHZ
#define CONFIG_OSC_AUTOCAL_RC2MHZ_REF_OSC   OSC_ID_RC32KHZ
#define CONFIG_USBCLK_SOURCE                USBCLK_SRC_RCOSC
#define CONFIG_OSC_RC32_CAL                 48000000UL
#define CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC  OSC_ID_USBSOF

With the Basic usage of the System Clock Management service

#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLL
// Fpll0 = (Fclk * PLL_mul) / PLL_div
#define CONFIG_PLL0_SOURCE          PLL_SRC_XOSC
#define CONFIG_PLL0_MUL             (32000000UL / BOARD_XOSC_HZ)
#define CONFIG_PLL0_DIV             1
// Fbus = Fsys / (2 ^ BUS_div)
#define CONFIG_SYSCLK_PSADIV        SYSCLK_PSADIV_1
#define CONFIG_SYSCLK_PSBCDIV       SYSCLK_PSBCDIV_1_2

and with the Advanced use case - Peripheral Bus Clock Management (XMEGA)

#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLL
// Fpll0 = (Fclk * PLL_mul) / PLL_div
#define CONFIG_PLL0_SOURCE          PLL_SRC_XOSC
#define CONFIG_PLL0_MUL             (32000000UL / BOARD_XOSC_HZ)
#define CONFIG_PLL0_DIV             1
// Fbus = Fsys / (2 ^ BUS_div)
#define CONFIG_SYSCLK_PSADIV        SYSCLK_PSADIV_1
#define CONFIG_SYSCLK_PSBCDIV       SYSCLK_PSBCDIV_1_1
#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_RCOSC
#define CONFIG_OSC_RC32_CAL         48000000UL
#define CONFIG_OSC_AUTOCAL          OSC_ID_RC32MHZ
#define CONFIG_OSC_AUTOCAL_REF_OSC  OSC_ID_USBSOF

the timer doesn't even start.
I think the program in last two cases stops somewhere in sysclk_init().

The 32768Hz Xtal is working, I see 32.7KHz 270 mVpp on CPU pin TOSC2.

For development tools I use Atmel studio 6.0.1996 SP2, ASF 3.5.0 and Flip 3.4.7.

My question is: why the configurations with SYSCLK_SRC_PLL aren't working.

Any help would be appreciated!

Thanks,

Bogdan.

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The PLL won't lock, as the XMEGA-A3BU does not have an external XTAL attached. There's a 32KHz crystal attached to the separate TOSC crystal inputs for the RTC, but the PLL can only source from the primary XTAL source pins.

- Dean :twisted:

Make Atmel Studio better with my free extensions. Open source and feedback welcome!

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Thank you for your quick answer.

As I can see in doc8362.pdf (ATxmega256A3BU) in Figure10-1, the 32.768 kHz crystal on TOSC can be connected to PLL.

From 10.3.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and
enables a dedicated low frequency oscillator input circuit. A low power mode with reduced voltage
swing on TOSC2 is available. This oscillator can be used as a clock source for the system
clock and RTC, and as the DFLL reference clock.

Is documentation wrong, or I'm missing something ?

Bogdan.

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I think even at the highest multiplication factor the PLL's minimum output frequency is too high to run from a 32kHz reference.

EDIT: however, if you've got a 32kHz crystal, you can use that as the DFLL source on one of the internal rcoscs.

Jeff Nichols

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I think the clock routing diagram connection between the TOSC and the PLL is a mistake. While it's possible to run the system clock off the TOSC crystal directly (configure the system clock to use XOSC, configure XOSC to source from TOSC) the PLL module doesn't support TOSC, only:

- 2MHz internal oscillator
- 32MHz internal oscillator divided by 4
- 0.4MHz - 16MHz crystal oscillator
- External clock

The alternative is to use the TOSC as a DFLL reference for a faster internal oscillator, which you can then PLL up.

- Dean :twisted:

Make Atmel Studio better with my free extensions. Open source and feedback welcome!

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Thanks for the explanation.

Bogdan.

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Hi,

I have also the XMEGA-A3BU Xplained board with ATxmega256A3BU and i'm trying to set the system clock to the external 32768 crystal directly.
Despite my efforts, the TOSC clock cannot be enabled (the XOSCRDY bit is never set).

My code is:

    OSC.CTRL = OSC_XOSCEN_bm;
    
    OSC.XOSCCTRL |= OSC_XOSCSEL_32KHz_gc;

    while ((OSC.STATUS & OSC_XOSCRDY_bm) == 0);

    CCPWrite(&CLK.CTRL, CLK_SCLKSEL_XOSC_gc);

    OSC.CTRL &= ~OSC_RC2MEN_bm;

The 32768 crystal is working, i have checked it with a scope.

Can anyone tell me what i am missing?

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Hi to everybody,

 

after a long time I decided to use again my xmega256a3bu board for fun.

 

In my project I would like to run a PLL clock with 32 MHz internal oscillator but unfortunately it doesn't work.

 

I use Ateml Studio 6.2 version and i tried all kind of compiler optimization.

 

At below I attached my code:

#define F_CPU 2000000UL  // set clock value 2MHz

#include <util/delay.h>

 

int main(void){
    
    // led 0 in output
    PORTR_DIR &= 0x00;        //(clean port)
    PORTR_DIR |= 0x01;        // Pin 0 & 1 of PORT R in writing  
    PORTE_DIR &= 0x00;        // all PORT E in reading  NB! (see pag. 149 of ATXMEGA_manual.pdf)    

 

    // ***   PLL with src=32MHz ***

 

    OSC_CTRL|=OSC_RC32MEN_bm;

    OSC_CTRL &= ~(OSC_RC2MEN_bm | OSC_XOSCEN_bm | OSC_PLLEN_bm); //Disable the unused oscillators

    while(!(OSC_STATUS & OSC_RC32MRDY_bm));

 

    OSC_PLLCTRL= OSC_PLLSRC1_bm |OSC_PLLDIV_bm; //select internal 2MHz oscillator as PLL clock source, PLL multiplication factor as 8 (2*8= 16MHz)

    OSC_CTRL=OSC_PLLEN_bm; //enable PLL

 

    while(!(OSC_STATUS & OSC_PLLRDY_bm)); //wait until PLL is locked to desired frequency and ready to use

 

    CCP=0xd8; //write Configuration Change Protection register

    CLK_CTRL=CLK_SCLKSEL2_bm; //select PLL as system clock source

 

    CCP=0xd8; //write Configuration Change Protection register

    CLK_PSCTRL=CLK_PSADIV_4_gc; //select Prescaler A as 4, Prescaler B and Prescaler C as 1, Clksys=32MHz, Clkper4=Clkper2=Clkper=Clkcpu=8MHz

 

    while(1) {    

       _delay_ms(1000);
       PORTR_OUT ^= 0x01;    // blink led 0    

  
    }  

}

 

When I run this code the led holds turn on  but it doesn't blink. Could someone check my code?

 

Just another question...

By reading the datasheet i was able to find the register where is possible to divide by 4 the 32MHz internal oscillator (PLLCTRL has only bit 5 to divide by 2 the PLLSRC). Was I wrong? 

 

Thanks in advance!

 

 

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@JetJet, what does your post have to do with using the TOSC as the system clock and/or PLL source?  You should have created a new topic.

 

By reading the datasheet i was able to find the register where is possible to divide by 4 the 32MHz internal oscillator

The input to the PLL from the RC32M is divided by four.  This is not configurable.  Regarding your code, what is the current clock source when the following executes:

    OSC_CTRL|=OSC_RC32MEN_bm;
    OSC_CTRL &= ~(OSC_RC2MEN_bm | OSC_XOSCEN_bm | OSC_PLLEN_bm); //Disable the unused oscillators
    while(!(OSC_STATUS & OSC_RC32MRDY_bm));

 

Greg Muth

Portland, OR, US

Atmel Studio 7.0 on Windows 10

Xplained/Pro/Mini Boards mostly

 

 

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Hi Greg_Muth,

 

thanks for your quick answer and my apologize if I was wrong to write here in the "Sysclk_init problem" topic (I will keep in mind for the future).

 

 

The input to the PLL from the RC32M is divided by four.  This is not configurable.

Do you mean that if I choose 32 MHz as clock source for PLL then resultant frequency will be 32/4=8MHz?

 

Regarding my code, clock before to set 32 MHz internal clock was 2 MHz internal clock (default clock), right?

I found these rows on another post and I can guess that as soon as 32 MHz internal oscillator is stable, led should blink correctly.

Was I wrong to change the clock in my code? 

 

The aim of this project is just to check the ability to set different clock throught the blink of a led. If I change the clock in a correct way then the led will change frequency.

 

 

Best regards,

JetJet

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Hello,

 

I am not used to write post in a forum so my apologize if I attached my question in a not inherent topic (I found the information about PLL and I have an issue about that so I decided to post here my question)

 

Could someone help me to redirect my question in right way in this forum? Should I open a new topic as suggest me from Greg_Muth

 

Any hint about my question?

 

In case my question would be unclear. please feel free to write me to solve question.

 

Thanks in advance,

JetJet

 

 

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Do you mean that if I choose 32 MHz as clock source for PLL then resultant frequency will be 32/4=8MHz?

Yes.

 

Regarding my code, clock before to set 32 MHz internal clock was 2 MHz internal clock (default clock), right? 

Right, but you disable the RC2M oscillator while you are waiting for the RC32M to become ready.  Lucky for you the XMEGA hardware will not let you disable the current clock source.

 

Greg Muth

Portland, OR, US

Atmel Studio 7.0 on Windows 10

Xplained/Pro/Mini Boards mostly