I'm using a AT32UC350512 in a circuit I designed with the intent of using an ADC input to be processed to drive a DAC output. My circuit has an independent VDDANA though a shared GND/GNDANA across the entire design. I am getting predicatable ADC measurements and predictable DAC measurements, though both are affected by a strange "noise" on the VDDANA supply.
When running my code, I see a 200 mVp-p sawtooth fluctuation on my VDDANA that is occurs the instant either the ADC, or the DAC or both is enabled with the ADCEN or DACEN register. The signal fluctuation is a sharp rising edge with a 150-20us linear falling edge.
I'm using ADCREF0 as the reference for both ADC and DAC and unfortunately I realized I was violating a design rule by using 3.3V for ADCREF0. I changed this to 2.0V but I still see the same sawtooth fluctuation on VDDANA.
Interestingly, when I change the ADC reference to use ADCREFP/ADCREFN, the fluctuation of VDDANA significantly decreases... (note, I was also using 3.3V for ADCREFP before changing it to 2.0V).
My VDDANA supply is a Microchip MIC5205-3.3YM5-TR linear regulator so it's not switching noise I believe.
I'm at a loss as to what could be causing this. Even if I'm not driving any loads or really doing anything that should bog down my analog rail, I'm still seeing this 200mv fluctuation.
Any ideas of what might be causing it or what I could try to debug?