AVR Errata - Unpublished, and other "Gotchas"

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The only error is the 3 instead of 2 cycles. I think their use of the word "jump" is just in the general sense meaning "some opcode that gets you from one place to another". Both JMP and RJMP achieve that. I agree that if they'd said "The vector is normally a JMP to the interrupt routine, and this jump takes three clock cycles. " then that would be wrong. (obviously the 3 cycle thing is an error though).

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Device: ATtiny167
Datasheet Revision: 8265C-AVR-03/12
Feature: Dynamic Clock Switch

The code section in datasheet page 34 (non-watchdog) & page 36 (with watchdog) has a missing section of code & the CLOCK_AVAILABILITY definition.

The missing definition to be added:

#define CLOCK_AVAILABILITY 0x03	

The missing section of code:

	//NEW Added: Request for Clock Availability
	CLKSELR = ((sut << 4) & 0x30) | (clk_number & 0x0F);
	CLKCSR = 1 << CLKCCE;
	CLKCSR = CLOCK_AVAILABILITY;

Without the above section of code & definition, the CLKRDY bit in CLKCSR will NEVER be set thereby putting your code in endless loop in:

	// Wait for clock validity
	while ((CLKCSR & (1 << CLKRDY)) == 0);

Atmel support has confirmed this error & the above missing section of code was provided by them.

My complete & tested code is below:

#define F_CPU	5000000UL

#include 
#include 
#include 

#define CLOCK_RECOVER 0x05	
#define CLOCK_ENABLE 0x02	
#define CLOCK_SWITCH 0x04	
#define CLOCK_DISABLE 0x01	
#define WD_ARL_ENABLE 0x06	
#define CLOCK_AVAILABILITY 0x03	


#define WD_2048CYCLES 0x07

void ClockSwitching(unsigned char clk_number, unsigned char sut)
{
	
	unsigned char previous_clk, temp;
	// Disable interrupts
	temp = SREG; asm ("cli");

	// Save the current system clock source
	CLKCSR = 1 << CLKCCE;
	CLKCSR = CLOCK_RECOVER;
	previous_clk = CLKSELR & 0x0F;
	
	// Enable the new clock source
	CLKSELR = ((sut << 4 ) & 0x30) | (clk_number & 0x0F);
	CLKCSR = 1 << CLKCCE;
	CLKCSR = CLOCK_ENABLE;
	
	//NEW Added: Request for Clock Availability
	CLKSELR = ((sut << 4) & 0x30) | (clk_number & 0x0F);
	CLKCSR = 1 << CLKCCE;
	CLKCSR = CLOCK_AVAILABILITY;
	
	// Wait for clock validity
	while ((CLKCSR & (1 << CLKRDY)) == 0);
	// Enable the watchdog in automatic reload mode
	WDTCR = (1 << WDCE) | (1 << WDE);
	WDTCR = (1 << WDE ) | WD_2048CYCLES;
	CLKCSR = 1 << CLKCCE;
	CLKCSR = WD_ARL_ENABLE;
	// Switch clock source
	CLKCSR = 1 << CLKCCE;
	CLKCSR = CLOCK_SWITCH;
	// Wait for effective switching
	while (1){
		CLKCSR = 1 << CLKCCE;
		CLKCSR = CLOCK_RECOVER;
		if ((CLKSELR & 0x0F) == (clk_number & 0x0F)) break;
	}
	// Shut down unneeded clock source
	if (previous_clk != (clk_number & 0x0F)) {
		CLKSELR = previous_clk;
		CLKCSR = 1 << CLKCCE;
		CLKCSR = CLOCK_DISABLE;
		CLKCSR = 0x80;	//Errata suggestion
	}
	// Re-enable interrupts
	SREG = temp;
}	


int main(void)
{
	DDRB |= (1 << PORTB0);
	PORTB &= ~(1 << PORTB0);
	
	ClockSwitching(0x0D, 0x02);
	
    while(1)
    {
        PORTB ^= (1 << PORTB0);
		_delay_ms(100);
    }
}

Once an engineer, forever an engineer

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Thanks for sharing, it is now saved in my bottomless pit of AVR stuff. :-)

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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ATmega644(P) and ATmega1284(P):

High slewrate data on RxD0 disturbs the crystal oscillator in the AVR when it's not set to "Full swing" with the fusebits.
So either reduce the slewrate on RxD (using 10k - 100pF Low pass filter), or set the oscillator to full swing.

All credits to njepsen on the MCSelec-forum
http://www.mcselec.com/index2.ph...

I am just the messenger ;)

Nard

A GIF is worth a thousend words   She is called Rosa, lives at Mint17.3 https://www.linuxmint.com/

Dragon broken ? http://aplomb.nl/TechStuff/Dragon/Dragon.html for how-to-fix tips

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Atmega48A/88A/168A/328A+PA datasheet
doc: 8271G-AVR-02/2013

In section 20.7 there is a bug in the example

The assembly example is:

USART_Receive:
; Wait for data to be received
in r16, UCSRnA
sbrs r16, UDREn
rjmp USART_Receive
; Get and return received data from buffer
in r16, UDRn
ret

Here the USART Data register Empty flag is checked instead of the USART Receive Complete flag.
The fun part is that the C code example below that does have the correct code:

unsigned char USART_Receive( void )
{
/* Wait for data to be received */
while ( !(UCSRnA & (1<<RXCn)) )
;
/* Get and return received data from buffer */
return UDRn;
}
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AT90CAN128: aborting a pending MOb can leave CONMOB in an unexpected state

I am not sure what kind of bug this is: could be a hardware bug or could be Atmel's library at90CANlib_3_2 being buggy AND misleading.

The library's procedure to abort a MOb that was pending consists on writing 0 to the CONMOB bits. Also, the library depends on those bits being 0 to detect a MOb as being free.

Turns out that a failed MOb (e.g. because of bus errors) will retry its process, and if its CONMOB is overwritten with 0 in that situation there is a rare chance that the CONMOB will jump back to its old value. So any routine testing for CONMOB==0 will consider the MOb busy. Result: a MOb leaked and unusable until reset.

I wrote Atmel about this and their answer was that:

Quote:
If you want to abort CAN communications, I would instead recommend using ABRQ in CANGCON as the means to abort. CANCDMOB is not affected by the abort, so you would still have to manage it.

... but that is not a good solution, because ABRQ aborts all MObs. I only wanted to abort one MOb.

Also they said, ...

Quote:
CANCDMOB really does not indicate that a MOB is "free" in the sense that it is ready for the next transmission - other bits indicate this; the user manual is clear that CONMOB bits are not cleared once communication is performed...

Which is true according to the documentation, which mentions that CANEN is the register to check for availability of MObs. But that means that the library is pretty b0rked, since it never even refers to the CANEN registers.

Also, the manual mentions repeatedly that the CONMOB is not expected to change by itself, not even after a reset. Which makes me think that this is actually a hardware bug (no?).

Anyway, my minimal workaround is: when aborting a MOb, write 0 to CONMOB, check that the corresponding CANEN bit is 0, and rewrite the 0 to CONMOB.
Alternatively, to search for free MObs, stop checking CONMOB and switch to checking CANEN.

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ATtiny13A datasheet 8126F-AVR-05/12 chapter 7.5.1.

BODCR - BOD Control Register bitnames are labeled as BODS and BODSE, while in the tn13Adef.inc are labeled as BPDS and BPDSE.

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Typo in t25/45/85 datasheet, page 150, table 20-7. The rightmost column should read "Signature Byte 2" instead of 0.

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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The low power oscillator itself is a bug imho.  I have seen it cause all manner of glitchy, impossible to debug problems, which are magically cured by going back to the full swing oscillator.

 

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Two typing errors in ATmega64M1 datasheet (7647K–AVR–12/13 )

 

 

19.2.2 Current Source for Low Cost Traducer
An external transducer based on variable resistor can be connected to the current source. This ca be for instance:
A thermistor, or temperature-sensitive resistor, used as a temperature sensor
A CdS photoconductive cell, or luminosity-sensitivity resistor, used as a luminosity sensor.
Using the current source with this type of transducer eliminates the need for additional parts otherwise required in resistor
network or Wheatstone bridge.

 

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Many AVR8 datasheets, including modern versions for e.g. Mega48 family and Mega164 family, have the "I/O pin input hysteresis vs. VCC" graph in Typical Characteristics scaled in millivolts (mV).  It should be volts (V), as in e.g. Tiny1634 sheet.

 

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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ATtiny4/5/9/10 datasheet.

link: http://www.atmel.com/images/atme...

page 146, section 16.4.2

SST - Serial STore to data space using indirect addressing

 

This binary value is wrong....

"DS[PR] ← data 0110 0000 PR ← PR + 1 Post increment"

 

It should be...

"DS[PR] ← data 0110 0100 PR ← PR + 1 Post increment"

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Device: MEGA644P family

Summary: Datasheet errata

 

Datasheet assembler examples (notably the USART) do not appear to have been updated to reflect that some registers are now outside the 'magic 32' where in and out instructions work and therefore lds and sts need to be sued, and the example code will throw errors.

It's me again...

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Datasheet assembler examples (notably the USART) do not appear to have been updated to reflect that some registers are now outside the 'magic 32' where in and out instructions work and therefore lds and sts need to be sued, and the example code will throw errors.

Thank you.

 

Note that the 'magic 32' are for the single-instruction bit-manipulation and bit-testing instructions like SBI/CBI/SBIS/SBIC.  Instructions like IN/OUT will work on all 64 I/O registers.

 

 

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"Read a lot.  Write a lot."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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stub does your datasheet contain a little note at the bottom of the examples which says:

 

Note: 1. See “About Code Examples” on page 8.

which in turn says

3.2 About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
The code examples assume that the part specific header file is included before compilation. For
I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and
"STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

 

Anyway assembler tragics use macros to overcome that sort comings wink

AVR001: Conditional Assembly and portability macros
 

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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Device: XMEGA128A1U

Summary: Analog Comparator silicon errata

 

The XMEGA128A1U (and probably XMEGA64A1U) does not make AC1OUT signals available on PA6 and PB6.

 

Not a problem if just migrating from older XMEGA128A1 device. Could bite you if migrating from a different AU device (A4U in my case).

 

Workaround: AC ISR to toggle output pin if you can tolerate the latency.

 

 

 

 

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balisong42 wrote:
Workaround: AC ISR to toggle output pin if you can tolerate the latency.
Proposed alternate work-around (transparency : I haven't tried it)

The event system can route an event sourced by AC to be sunk by a port pin.

 


http://www.atmel.com/products/microcontrollers/avr/avr_xmega.aspx?tab=documents

Atmel AVR XMEGA AU Manual
(file size: 7.2MB, 478 pages, revision F, updated: 04/2013)

http://www.atmel.com/Images/Atmel-8331-8-and-16-bit-AVR-Microcontroller-XMEGA-AU_Manual.pdf

13. I/O Ports

(page 146, bottom)

13.10 Clock and Event Output
It is possible to output the peripheral clock and any of the event channels to the port pins (using EVCTRL register). This
can be used to clock, control, and synchronize external functions and hardware to internal device timing. The output port
pin is selectable. If an event occurs, it remains visible on the port pin as long as the event lasts; normally one peripheral
clock cycle.

 

Edit : manual

 

"Dare to be naïve." - Buckminster Fuller

Last Edited: Sat. Mar 11, 2017 - 06:28 AM
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Device: ATmega328PB datasheet (complete) 40001906A, (C) 2017

Summary: PD0 incorrectly listed as RXD1 (USART1 Input Pin) on page 98 under "17.3.3. Alternate Functions of Port D". Correct assignment for PD0 is RXD0 (USART0 Input Pin) as elsewhere in datasheet (including "Table 6-1. PORT Function Multiplexing"). Also makes ATmega328PB Xplained Mini schematic more logical: unlikely to use USART0 for TXD and USART1 for RXD.

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Device: ATmega328PB Xplained Mini User Guide 42469B, updated 2015-08

Summary: PD1 and PD0 ATmega328PB pins incorrectly swapped in "Table 2-10 J104 USART Header" on p.17. (ATmega328PB Xplained Mini schematic A09-2523 Rev. 4, 04.01.2017, is correct.)

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