Idle Task and Graphics performance

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Hello freaks, I have a kernel I am designing and I have a task that updates the ILI9341 display.  Performance wise, the Idle(display) task has 88% of the CPU time but my screen only updates 2 - 3 fps.

The remaining system has IRQ's in the range of 25000 irqs a second.

 

Thanks for any help in solving this issue.

William

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25,000? Most systems would run a 10ms or perhaps 1ms tick so would have 100 or 1,000 interrupts per second.

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Hello Clawson, the context switch occurs 10,000 a second.  Turning down helps but I can't understand the performance hit when the Idle , i.e. graphics task has 88% of the CPU time.  Is there a link between irqs and the DMA which I'm using to drive the display?

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How are you measuring the 88%? If your isr task is chewing up 50% of actual time then 88% as measured by your isr is half in actual time. With the Cortex M3/4 it has a cycle counter in the debug unit that you can use to measure fairly accurately actual time. Does the AVR32 have a similar thing?

The old skool technique I use to measure execution time is to control a port pin - set high on entry to a function, set low on exit and use an oscilloscope or logic analyser to measure. That way you can measure the execution time of the function and how often it gets called. You can also get an idea of the timing jitter and variance of the execution time. No 'scope or logic analyser? Salaea Logic clones can be got for around $10usd. The best money you'll ever invest if you're playing around with micros.

 

Here's something a good friend on mine wrote:

http://www.fliptronics.com/ESC_2...

 

Last Edited: Tue. Mar 7, 2017 - 09:43 PM
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Fianawarrior wrote:
Is there a link between irqs and the DMA which I'm using to drive the display?
Maybe

Is the MPU mis-configured?

http://www.atmel.com/products/microcontrollers/avr/32-bitavruc3.aspx?tab=documents

AT32UC3C Series Complete
(file size: 19.6MB, 1316 pages, revision D, updated: 03/2012)

AT32UC3C0512C, AT32UC3C0256C, AT32UC3C0128C, AT32UC3C064C, AT32UC3C1512C, AT32UC3C1256C, AT32UC3C1128C, AT32UC3C164C, AT32UC3C2512C, AT32UC3C2256C, AT32UC3C2128C, AT32UC3C264C
http://www.atmel.com/Images/doc32117.pdf

Table 4-4. Priority and Handler Addresses for Events

Could count each event to get some more data; five of the events are interrupts.

An AVR ONE! and IAR EW AVR32 could trace all then might be able to locate the cause without additional source code.

Atmel Studio has a limited trace capability for AVR32 UC3 :

http://www.atmel.com/webdoc/GUID-ECD8A826-B1DA-44FC-BE0B-5A53418A47BD/index.html?GUID-ECF8CABA-419E-4E99-8D7A-7C0CCDBECF98

http://www.atmel.com/webdoc/GUID-ECD8A826-B1DA-44FC-BE0B-5A53418A47BD/index.html?GUID-DE11D810-D452-4617-81DA-FA92FD63F6AD

 

Edit : Atmel Studio

 

"Dare to be naïve." - Buckminster Fuller

Last Edited: Tue. Mar 7, 2017 - 11:32 PM
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Kartman wrote:
Does the AVR32 have a similar thing?
Yes for UC3 though AVR32 AP7 had several more performance counters.

http://www.atmel.com/products/microcontrollers/avr/32-bitavruc3.aspx?tab=documents

Atmel AVR 32-bit Architecture Manual Complete
(file size: 5108318, 377 pages, revision D, updated: 04/2011)

http://www.atmel.com/Images/doc32000.pdf

...

COUNT - Cycle Counter Register
The COUNT register increments once every clock cycle, regardless of pipeline stalls and
flushes. The COUNT register can both be read and written. The count register can be used
together with the COMPARE register to create a timer with interrupt functionality. The COUNT
register is written to zero upon reset and compare match. Revision 3 of the AVR32 Architecture
allows some implementations to disable this automatic clearing of COUNT upon COMPARE
match, usually by programming a bit in CPUCR. Refer to the Technical Reference Manual for
the device for details. Incrementation of the COUNT register can not be disabled. The COUNT
register will increment even though a compare interrupt is pending.

...

COUNT is System Register 66.

 

"Dare to be naïve." - Buckminster Fuller

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Hi Kartman, the 88% is the total processing time available to the Idle task that in turn uses all the time it can get.  I have calculated the time spent by the Ideal Task to be 88%.

 

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Regardless, the first step in optimising is to get some hard evidence. Pinpoint what is taking the time and understand why. It might turn out to be that the interface to the display is simply slow. You could calculate the time, but that is labourious - much easier to measure.