[TUT] Newbie's Guide to AVR Interrupts

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Knowing that each address of program memory is 16 bits wide and PC is less than 16 bits wide, why the address of each interrupt vector differs from the previous one by two?
For instance:
the INT1 vector is located at address $0004 and the INT2 vector is located at address $ 0006.

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Thanks for posting this. Very useful.

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Thanks for this post :-).

One minor comment.

As i understand AVR8 and AVR32 uses a different interrupt handling mechanism (correct me if i am wrong), and if that is the case may i request you to add a small note that this is for AVR8 (again, this i assume :) ?

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Quote:

i request you to add a small note that this is for AVR8

Take a step back to the first page. This Tutorial Forum is part of the 8 bit section. You can see that in the link to here:

AVR Freaks Forum Index » AVR (8-bit) Technical Forums » AVR Tutorials

ALL the articles here are about AVR8. AVR32 stuff is separate. As far as I know they haven't chosen to setup a tutorial forum.

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I have a question about using:
ATOMIC_BLOCK(ATOMIC_FORCEON){}

Say I have timer2 set up to overflow once per second and the following code:

volatile unsigned long RealTimeSeconds;		
ISR(TIMER2_OVF_vect)
{
	RealTimeSeconds++;
}

Similarly to the tutorial, I want to access RealTimeSeconds from my main code, and want to be sure the ISR doesn't fire mid-read (however unlikely), but I want to access it from multiple routines.

Rather than doing this at each point I want RealTimeSeconds:

ATOMIC_BLOCK(ATOMIC_FORCEON){
	blah = RealTimeSeconds;
}

Can I do this?

unsigned long getSeconds()
{
	ATOMIC_BLOCK(ATOMIC_FORCEON){
		return RealTimeSeconds;
	}
}

blah = getSeconds();

Also, if the overflow occurs while the atomic code is executing, will the ISR be skipped entirely (effectively losing a second of time keeping) or just held off until the atomic block is done?

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Yes, that's fine - although slightly slower since you then have the overhead of the function call (unless the compiler inlines it).

If the flag is set while interrupts are disabled it will then execute the ISR when the block ends - but if multiple occurrences of the same event cause the flag to be set, the ISR will only be run.

- Dean :twisted:

Make Atmel Studio better with my free extensions. Open source and feedback welcome!

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Thanks, that's what I was assuming. I may just do it the original way though since wrapping the return statement generates this harmless but annoying warning:
control reaches end of non-void function [-Wreturn-type]

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Better option:

unsigned long getSeconds()
{
   unsigned long temp;

   ATOMIC_BLOCK(ATOMIC_FORCEON){
      temp = RealTimeSeconds;
   }

   return temp;
}

Betterest option: use the above, but switch to the standard types from C99.

- Dean :twisted:

Make Atmel Studio better with my free extensions. Open source and feedback welcome!

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Quote:

wrapping the return statement generates this harmless but annoying warning:
control reaches end of non-void function [-Wreturn-type]

try:

unsigned long getSeconds()
{
   unsigned long retval;
   ATOMIC_BLOCK(ATOMIC_FORCEON){
      retval = RealTimeSeconds;
   }
   return retval;
} 

I bet you find the compiler generates exactly the same code but the warning is suppressed. Consider making the function "static inline" in a header file too so you don't have the CALL/RET overhead as long as it's not called in hundreds of places.

EDIT SNAP! (great minds think alike - we both posted at 6:28!)

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Thanks. Would the C99 Data type be an "unsigned long int" rather than just an "unsigned long"?

I'm favoring code size, so I'll leave it as is. I tested it as a static inline and got a 50 byte increase.

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The exact-width types from - they make your code easier to grok and somewhat more portable, since you can be sure that a "uint32_t" is an unsigned 32-bit integer regardless of platform.

See:
https://en.wikibooks.org/wiki/C_...

- Dean :twisted:

Make Atmel Studio better with my free extensions. Open source and feedback welcome!

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Quote:
Thanks. Would the C99 Data type be an "unsigned long int" rather than just an "unsigned long"?
"unsigend long" and "unsigned long int" are identical. In the first the "int" is implied.

Regards,
Steve A.

The Board helps those that help themselves.

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i still don't get this part, please explain more, what does this mean..

Quote:

3) There's another subtle bug in the above code sample; it's possible at the machine code level for an interrupt to occur half way between the fetching of the two bytes of the integer variable MyValue, causing corruption if the variable's value is altered inside the ISR. This can be avoided by making the fetching of the variable's value in the main program code "atomic", by disabling the global interrupt enable bit while the fetching is taking place. In avr-libc this can be done in the following manner:

#include  
#include  

volatile int MyValue; 

ISR(SomeVector_vect) 
{ 
   MyValue++; 
} 

int main(void) 
{ 
   SetupInterrupts(); 

   int MyValue_Local; 

   do 
   { 
      ATOMIC_BLOCK(ATOMIC_RESTORESTATE) 
      { 
         MyValue_Local = MyValue; 
      } 
   } while (MyValue_Local == 0) // Wait for interrupt 

   TurnOnLED(); 
}

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Quote:

i still don't get this part, please explain more,

Consider the code:

#include 

volatile int MyValue;

ISR(SomeVector_vect)
{
   MyValue++;
}

int main(void)
{
   SetupInterrupts();

   while(1) {
     if (MyValue == 0x100) {
        TurnOnLED();
     }
   }
} 

C guarantees that MyValue starts at 0 so you'd have thought that after 256 (0x100) interrupts the LED would be turned on - right?

So now consider the case when MyValue is holding 0x00FF. The code that does the "if (MyValue == 0x100) {" is going to look something very like:

.L9:
//==> 		if (MyValue == 0x100) {
	lds r24,MyValue
	lds r25,MyValue+1
	cp r24,__zero_reg__
	sbci r25,1
	brne .L9

So the compiler collects the value in MyValue into registers R25:R24 then makes a comparison of this with 0x100.

Now consider that it has done the first of the two LDS there:

	lds r24,MyValue

At this moment R24 contains 0xFF. Then the interrupt code occurs and it heads off to the ISR():

//==> 	MyValue++;
	lds r24,MyValue
	lds r25,MyValue+1
	adiw r24,1
	sts MyValue+1,r25
	sts MyValue,r24

That takes 0x00FF and increments it to 0x0100 and stores it back. So the "MyValue" location now holds 0x00 and MyValue+1 holds 0x01. It then returns from the interrupt to the second LDS in:

//==> 		if (MyValue == 0x100) {
	lds r24,MyValue
	lds r25,MyValue+1
	cp r24,__zero_reg__
	sbci r25,1

Already this R24 holds 0xFF and now it loads the value from MyValue+1. That contains 0x01. So in total R25:R24 hold 0x01FF and not the 0x0100 we're hoping to see. So the if() test is false and the LED is not turned on. Now the interrupt fires again and this time 0x0100 in MyValue is incremented to 0x0101. On return from ISR() it now does the if() test in main() again. Only this time it succeeds in correctly reading R25:R24 as 0x0101. That does not == 0x100 either so again the LED is not lit.

Because of "mis-read" of MyValue the actual 0x0100 value was never seen so the if() test was never true and the LED never turned on (or at least not until MyValue has incremented and wrapped).

That is why you need atomic protection. In avr-gcc you do that with ATOMIC_BLOCK() which effectively says "just while I'm doing this one thing turn the interrupts off, you can turn them on when I've finished". So the code inside the ATOMIC_BLOCK that takes a copy of MyValue into MyValue_Local is guaranteed not to be interrupted and therefore cannot "mis-read" the variable by being interrupted part way through. If MyValue had 0x00FF it will still have that until at least the end of the ATOMIC_BLOCK and once it has 0x100 it will again have it for the entire reading process.

That is why you need atomic access protection when reading variables that are more than a byte wide. If MyValue had been char/uint8_t yo wouldn't have needed to worry as LSD/LD or whatever that would be used to read a single byte cannot be interrupted mid-way through.

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so this is the mean of atomic?

Quote:
"just while I'm doing this one thing turn the interrupts off, you can turn them on when I've finished".

so can i use that for usart instead using interrupt for sending a bit?

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Quote:

so this is the mean of atomic?

Well atomic means "uninterruptible" (effectively). (it dates from a time when atoms could not be divided - now we know they can be - but on the whole CPU opcodes cannot be, like the old view of atoms.
Quote:

so can i use that for usart instead using interrupt for sending a bit?

I haven't got the first idea what that question means or how it relates in any way to the question of atomicity. Are you talking about implementing "soft UART" by bit-banging an IO pin in an interrupt? If so I guess it's true that the byte that is being sent would not want to be updated after only 5 or the 8 bits had been transmitted or similar.

Maybe try your question in your native language?
(Mungkin mencoba pertanyaan Anda dalam bahasa asli Anda?)

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i mean, i have a code that using timer interrupt, but i dont used usart interrupt, so in some periode of time usart has stop/error and i know it maybe because when the uC sent the data my code interrupt that for the timer, so if i used atomic is that same like i use interrupt for usart?

can i use this

ATOMIC_BLOCK(ATOMIC_RESTORESTATE) 
      { 
void kirim(char *x)
{
	while(*x>0)
	{
		while (!( UCSRA & (1 << UDRE )));
		UDR = *x++;

	}
}

instead of interrupt uart?

and one more question. i forgot to put
#include
but i put
#include
only and i used interrupt

SEI()

but it compiled with no error.
i never see what inside atomic.h but why i can use interrupt when i forget to put #include instead #include

and help me here too :)
http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&p=1103673#1103673

ps:

Quote:
Maybe try your question in your native language?
(Mungkin mencoba pertanyaan Anda dalam bahasa asli Anda?)

wow you can speak indonesian? or used google translate.. :) what does it means? can i used my native language, did you understand that?

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Quote:

instead of interrupt uart?

That depends what you are trying to achieve. The contents of your ATOMIC_BLOCK there are possibly going to take thousands and thousands of CPU cycles (it block on UDRE and outputs potentially multiple bytes) and the whole thing wil occur without interrupts enabled (that's the purpose opf ATOMIC_BLOCK). So your question is can you really afford to have the interrupts disabled for that length? During that time your timer interrupt will not be serviced.

As with anything to do with interrupts whether it be the ISR()s themselves or ATOMIC_BLOCK's in the main code each should aim to complete in just a few tens or hundreds of CPU cycles. This way no process can "hog" the CPU. Doing a while(UDRE) loop while interrupts aer disabled goes against this.

If you are saying you have a timer interrupt and code that inputs/outputs to the UART that is non-interrupt and that sometimes the UART code is intermittent it suggests that something in your timer interrupt handler is taking too long to complete.

In the limit a timer ISR() should be doing little more than setting a flag to say that some period has expired. The main() code can then service this flag and do any "long work" necessary. The downside of this design is that the main code may not "see" the flag for some while so the triggered process can be "late". If there things you need to do that really are time critical then do put that code into the ISR() but always consider how long they are going to delay the return from interrupt by. If a long time think of another way to implement it.

Quote:

wow you can speak indonesian? or used google translate.. Smile what does it means? can i used my native language, did you understand that?

I just used Google translate (I am a moderator so could see you were from Indonesia). My suggestion to you is that if you have difficulty with asking questions or describing your project then just write it in Indonesian then either post it here "as is" or use Google Translate yourself. If you don't I will anyway. You may find it easier to describe your problem if you just use your natural language.

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Which would you say is correct or more correct?

The I flag in the status register:
1) Globally activates all interrupts.
2) Permits/allows the AVR to process interrupts.

If I understand correctly, the global interrupt flag allows us to activate separate interrupts. It does not activate them, just allows us to go and activate each interrupt ourselves, in their respective control registers? If it is disabled, and we try to enable a separate interrupt we will be unable to do so? So I'm pretty sure 2) is correct. I just want make sure I correctly understood what I read in the manual.

Attachment(s): 

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Quote:

If I understand correctly, the global interrupt flag allows us to activate separate interrupts.

Where on earth did you get that idea?

Surely it's simple. The I flag is simply the global on off switch for the entire interrupting system. It most definitely does not allow the control of individual interrupt sources, you do that with individual control bits like UDRIE, TXCIE, TWIE, SPIE, etc.

While not always true it is very often the case that the names of the bits that control individual interrupts end in the letters "IE" which stand for Interrupt Enable.

To use interrupts you therefore enable one or more ??IE bits. For any that you do set you provide ISR code and then, when you are ready to turn the whole system on and start receiving calls to the ISR(s) you execute SEI which sets the I bit in SREG.

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Adding to Cliffs post:

The global interrupt flag controls if any interrupt will "fire", as in "an ISR will be called".

The individual interrupt enable bits on the individual peripherals controls the individual interrupts.

The individual interrupt enable bits are all "in parallel" with each other but in series with the global interrupt enable bit. So to get e.g. thr UART receive interrupt ISR executed both the individual interrupt enable bit for that needs to be set, and the global interrupt enable bit needs to be set.

Do note that the status bit in the UART status register that indicates an UART receive interrupt will be set even if the global interrupt enable bit is cleared.

In essence, the global interrupt enable bit controls if ISRs will be called or not.

If an interrupt condition arises while the global interrupt bit is cleared, but the individual interrupt enable bit in the peripheral is set - then when the global interrupt bit is set again the interrupt will actually fire (as in "the ISR will be called").

"He used to carry his guitar in a gunny sack, or sit beneath the tree by the railroad track. Oh the engineers would see him sitting in the shade, Strumming with the rhythm that the drivers made. People passing by, they would stop and say, "Oh, my, what that little country boy could play!" [Chuck Berry]

 

"Some questions have no answers."[C Baird] "There comes a point where the spoon-feeding has to stop and the independent thinking has to start." [C Lawson] "There are always ways to disagree, without being disagreeable."[E Weddington] "Words represent concepts. Use the wrong words, communicate the wrong concept." [J Morin] "Persistence only goes so far if you set yourself up for failure." [Kartman]

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As far as software interrupts go, AVR does not support software interrupts of any kind?

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Yes it does, read the datasheet (you can trigger an ext int by writing the port). I've never totally understood of what practical use that is.

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When using the mega16 and interrupts, is it necessary to set DDRD(PD2 and D3) as input and activate the pullup resistors?

LDI TMP, 0x00
OUT DDRD, TMP
LDI TMP, 0xFF
OUT PORTD, TMP

No there is no need to explain MCUCR, GICR, and SREG. I'm pretty sure DDRD does not need to be set(or that it is even possible) if we enable the pins as interrupt pins. I'm not sure about PORT.

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Pins used for interrupting need to be input but that's the default state anyway. As to whether you want pullup's or not depends on the external electronics. Is there an open connection that might float? If there is do you want it tied high or low in the quiescent state?

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Is it possible to have INT0 do one thing when you press down a button and do something else once the button is released? For example: You press down INT0 a LED turns on, you release INT0, the LED turns off. So, it does one thing during the falling edge and another during rising edge. Or would I have to use INT0 to turn the LED on and INT1 to turn the LED off.

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Quote:

Is it possible to have INT0 do one thing when you press down a button and do something else once the button is released?

It is seldom that "driving" an interrupt with a switch ios a good idea. Search this site and Google for "button bounce", "contact bounce", "button de-bouncing" and similar for A LOT of earlier discussions.

In short: When a button makes or breaks contact it will not produce one single clean rising or falling edge. Instead it will do several on-off-on-off... transitions during a few milliseconds, creating "false button presses".

No, don't ask. Do the searches, and read up first. It has been covered more times than we can count.

"He used to carry his guitar in a gunny sack, or sit beneath the tree by the railroad track. Oh the engineers would see him sitting in the shade, Strumming with the rhythm that the drivers made. People passing by, they would stop and say, "Oh, my, what that little country boy could play!" [Chuck Berry]

 

"Some questions have no answers."[C Baird] "There comes a point where the spoon-feeding has to stop and the independent thinking has to start." [C Lawson] "There are always ways to disagree, without being disagreeable."[E Weddington] "Words represent concepts. Use the wrong words, communicate the wrong concept." [J Morin] "Persistence only goes so far if you set yourself up for failure." [Kartman]

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Hi everyone

I am using an arduino atmega2560 development board.

My interrupts are set up correctly and fire up, but after inserting some small code in there to see that the program really enters the ISR, executes the code in the ISR and exits somehow doesn't occur.

heres my code:

#include 
#define F_CPU 16000000UL
#include 
#include 

int main(void)
{
  cli();
  DDRL |= 0xC7;
  DDRD |= 0x00;
  PORTD |= 0x04;
  //DDRG |= 0x20;
  
  //OCR0B = 1;
  TCNT0 = 0;
  TCCR0A |= 0x03;
  TCCR0B |= 0x03;
  TIMSK0 |= 0x01;
  
  //EICRA |= 0x20;
  //EIMSK |= 0x04;
  
  sei();
  
  while(1)
  {
   PORTL ^= 0x80;
   _delay_ms(1000);
  }
  
  return 0;
}

ISR(TIMER0_OVF_vect)
{
  PORTL ^= 0x40;
}

My LED freezes and doesnt blink, its just on. Somehow i feel that the ISR enters and just doesnt return.

Any help with this?

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Wrong thread- this is only to discuss the article in the first post - your general question about 2560 interrupts should be in AVR Forum.

Anyway I ran your code in the simulator with a breakpoint in the ISR which it hit after 16439 then 32823 cycles (so exactly 16384 cycles between).

As such I think this works. However at 16MHz one cycle is 0.0625us so 16384 cycles is 1,024us or roughly 1/1000th of as second. A human eye could never possibly see an LED flashing that fast - it will look like it's on all the time but at half brightness.

But as I say, if you want to continue this then let's do it in a new thread.

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Quote:

The interrupt source flag is usually cleared when the ISR fires.

 

How does one know when this is / isn't the case?

Building my dreams!

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bigpilot wrote:

Quote:

The interrupt source flag is usually cleared when the ISR fires.

 

How does one know when this is / isn't the case?

Because the datasheet says so.

 

And if this is about INT0 on a 32U4 then, yes, the datasheet says this:

The key sentence there being "The flag is cleared when the interrupt routine is executed".

 

But please don't pollute this tutorial thread with a cross posting hijack. Keep this in the thread you already started.

 

Moderator

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Thanks to abcminiuser for posting this.  As a newbie to AVR embedded programming, I thought I'd point out how frustratingly confused I was in reading it, though.  I read all the way through it (skimming over some parts like what I thought was assembler) before seeing the link to your site and the "updated pdf".  I'm not sure if anyone is aware that parts of the post are missing and that is what was causing my confusion.  It looks like there is probably some tag blocking software preventing the browser from rendering it... angle brackets needed to be escaped perhaps?  The library required for interrupts is missing.  I just see the #include.  Nothing after it.

 

Anyway, if this has been mentioned, I apologize.  I searched the thread for "tag" and "escape" thinking if someone had mentioned it previously, I wouldn't repeat it.

 

The pdf file is clear and helping me greatly with interrupts (where the datasheet had failed).  Thanks again

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You can thank the botched migration from the old forum to the new forum, not quite two years ago (after post #80).  You can look at the same thread on the legacy site here:

http://legacy.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&t=89843&start=all&postdays=0&postorder=asc&sid=c4bd73458c44c5af456a7e705db5ca3c

 

before seeing the link to your site and the "updated pdf".

Really?  It's the very first thing your read... er... skimmed over ;-)

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"Read a lot.  Write a lot."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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I understand this thread was four years old, but I thought I'd throw in a bone for updating it:  In newer AVRs, I specifically have in mind an ATmega168A, it _is_ possible to generate a software interrupt by setting an external interrupt pin as an output and then toggling its value.  Depending on the interrupt settings, this can fire an interrupt (See pg. 71 of the spec sheet (Rev. 8271C, dated 2010, so previous to the last post here...)).
 

Everything else remains marvelously helpful and informative.  Thanks.

 

S.

 

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In newer AVRs, I specifically have in mind an ATmega168A, it _is_ possible to generate a software interrupt by setting an external interrupt pin as an output and then toggling its value.  Depending on the interrupt settings, this can fire an interrupt (See pg. 71 of the spec sheet (Rev. 8271C, dated 2010,

That capability has always been possible, and has always been identified in datasheets for all devices in the AVR family, going back to the very first one, that AT90S1200, released in 1996:

http://www.atmel.com/Images/DOC0838.PDF

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"Read a lot.  Write a lot."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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Thank you very much for this thread... very helpfull to me! I am studying interrupts in AVR and reading this has clarified my mind a lot!
I would like to continue trying to understand more about the electrical signal and the hidden code regarding interrupts.
I am studying ATmega328P (datasheet: http://www.atmel.com/pt/br/Image...).

 

Building a project with avr-gcc, I can see three external files we have to combine in order to use interrupts: gcrt1.S, avr/sfr_defs.h, avr/interrupt.h and, in my case, avr/iom328p.h

I understand that, when in my source code I write something like

ISR(ADC_vect)
{
   //some code
}

The header "avr/interrupt.h" will be used to expand the macro to

void ADC_vect (void) __attribute__ ((signal,__INTR_ATTRS))
{
    //some code
}

The header "avr/iom328p.h" will be used to expand further to

void _VECTOR(21) (void) __attribute__ ((signal, __INTR_ATTRS))
{
    //some code
}

The header "avr/sfr_defs.h" will be used to expand the macro to

void __vector_21 (void) __attribute__ ((signal,__INTR_ATTRS))
{
    //some code
}

And finally this function is linked to the file "gcrt1.S", which defines, generically, the interrupt vectors' positions in flash memory.

(...)
    .macro    vector name
    .if (. - __vectors < _VECTORS_SIZE)
    .weak    \name
    .set    \name, __bad_interrupt
    XJMP    \name
    .endif
    .endm
    .section .vectors,"ax",@progbits
    .global    __vectors
    .func    __vectors
__vectors:
    XJMP    __init
    vector    __vector_1
    vector    __vector_2
(...)
    vector    __vector_21
(...)

In the datasheet we see that, if we leave BOOTRST and MCUCR as default, the interrupt vectors will be in flash memory and will start at 0x0000 (Reset) and follow table 16.1 until address 0x0032.

 

1. The first thing that comes in my mind is: where, in gcrt1.S, it is saying that __init is at address 0x0000, __vector_1 is at address 0x0002, __vector_2 is at address 0x0004, etc?

 

2. The second thing is regarding the interaction between the interrupt electric signal and the hardware: In electrical terms, I see the interrupt as a power generated by some hardware. For example, the ADC hardware generates some power (interrupt) in the 8-bit data bus line that connects it to the AVR CPU and the interrupt unit (figure below).

The way I think this is.. with interrupts enabled, when the ADC finishes the conversion, it sets the interrupt flag and sends a signal (electrical power (voltage*current)), via 8-bit register, to the interrupt unit. This unit (somehow) knows that this signal is coming from the ADC and tells the processor to stop what he is doing and go to the address 0x002A (table 16.1 from the datasheet). The processor goes to this address, finds a jump to __vector_21 that happens to be the start address of the ISR code.

 

 

 

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1) Where does it give any specific addressing? The only thing in gcrt1.S that has any connection to physical addresses is:

	.section .vectors,"ax",@progbits

that connects up to this in the avrN.x linker script file:

MEMORY
{
  text   (rx)   : ORIGIN = 0, LENGTH = 128K
  .text   :
  {
    *(.vectors)
    KEEP(*(.vectors))
    /* For data that needs to reside in the lower 64k of progmem.  */
    *(.progmem.gcc*)
etc.

Those two things in combination collude to make sure that:

__vectors:
	XJMP	__init

is located at physical location 0 in the ".text" segment (though for a bootloader a -Wl,-Ttext=0xNNNN" may have moved that to a non-0 location.

 

So far that ensures that the very first reset jump is at 0. However note that the opcode is not "RJMP" and it's not "JMP" but a predefined macro called "XJMP". It is defined in:

 

http://svn.savannah.nongnu.org/v...

 

as:

#if (__AVR_HAVE_JMP_CALL__)
  #define XJMP jmp
  #define XCALL call
#else
  #define XJMP rjmp
  #define XCALL rcall
#endif

So for AVRs above 8K (where __AVR_HAVE_JMP_CALL__ is defined) the instruction will be a 4 byteRJMP opcode while for the smaller AVR it will be a 2 byte RJMP. This is why in a micro like mega48 (4K) you see:

 

 

while for mega168/328/etc you see:

 

 

try to ignore Atmel's nasty habit of 16 bit addressing but see how the 4K micro table goes up in 2 byte steps while the 16K micro table goes up in 4 byte steps. This is because of the different usage of RJMP for the 4K micro (it does not have the JMP opcode) versus the use of JMP for the larger micros. So in:

__vectors:
    XJMP    __init
    vector    __vector_1
    vector    __vector_2

for the 8K or smaller micros this will compile as:

__vectors:
    RJMP    __init          ; @ byte 0x0000
    RJMP    __vector_1      ; @ byte 0x0002
    RJMP    __vector_2      ; @ byte 0x0004

while for 16K and above it will be:

__vectors:
    JMP    __init          ; @ byte 0x0000
    JMP    __vector_1      ; @ byte 0x0004
    JMP    __vector_2      ; @ byte 0x0008

So when you say:

JABBA_JOE wrote:
t is saying that __init is at address 0x0000, __vector_1 is at address 0x0002, __vector_2 is at address 0x0004, etc?
then true, the jump to __init is always at 0x0000 (except for -Wl,-section-start=.text=0xNNNN!) but it's not true to say the jump to __vector_1 is at 0x0002. It is either at 0x0002 for small AVRs and it is at 0x0004 for large AVRs (small-> <= 8K). So on for all the following. They are just "spaced" out according to the width of RJMP or JMP that is then used.
JABBA_JOE wrote:
it sets the interrupt flag and sends a signal (electrical power (voltage*current)), via 8-bit register, to the interrupt unit.

No that's not true. It is the ADIF bit itself that is the trigger. Every interrupt has some kind of flag (UART calls theirs RXC. TXC. UDRE for example). When the AVR finishes an opcode fetch part of it's logic (assuming I in SREG) is to scan all these interrupt flags in vector table order:

 

As soon as it comes to one that is set it triggers a PUSH of PC then loads PC with the vectorN location. As we've seen there's every chance it's going to find a JMP or RJMP when it fetches that next instruction - that is the way into the ISR handler.

 

If more than flag is set at the end of the opcode execution (and I is set) then it's the flag it comes to first that gets handled. The other flag(s) is ignored for the time being but when that handler eventually finishes and does RETI then the CPU will pick up and execute the next opcode after the interrupt return but when that opcode is finished it will now scan the table again and this time it will find the next flag that was previously se and handle that one and so on.

Last Edited: Fri. Nov 18, 2016 - 11:34 AM
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Thank you very much!!

 

I am trying to understand why did you say

clawson wrote:

try to ignore Atmel's nasty habit of 16 bit addressing

As far as I understood, the 16 bit addressing is the only reason why you can say that the change in address from 0x0000 to 0x0002 represents 4 bytes, and the change from 0x0000 to 0x0001 represents 2 bytes, right?

 

clawson wrote:

When the AVR finishes an opcode fetch part of it's logic (assuming I in SREG) is to scan all these interrupt flags in vector table order

So it means that the interrupt is a passive thing? I was thinking that the interrupt was an active thing... the harware would send actively the signal to the processor telling it to stop and manage the interrupt!

So it changes my understanding yes 

According to this, is correct to say that the processor is "polling" the interrupt after every opcode? This polling consumes some clocks?

 

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Yes, there is an entire population of computer engineers in planet earth who, almost to a man/woman always think of memory addressing in terms of bytes. So if you have data or opcode at N and something at N + 5 then you talke that "+ 5" to mean "5 bytes further on". Atmel, on the other hand have chosen to refer to the addressing of flash (but not RAM or EEPROM or IO or anything else) in terms of (16 bit) words. So for them "+ 5" actually means "10 bytes further on". This even causes confusion in the "Memories" dialog in AS7 where they have that long winded explanation about how if you enter foo=5 in the "flash" section it will actually be passed to GCC as "-Wl,...=10" because there will be an implicit doubling to convert the user WORD input into the BYTE offset that GCC likes to use.

 

If the entire world all addresses all memory in bytes none of this confusion would ever arise. Perhaps the classic is the positioning of bootloaders. A 16K AVR datasheet may tell you that one of the 4 available bootloader positions is 0x1C00 so folks are tempted to use -Wl,-section-start=0x1C00 and nothing works. When you think about it 0x1C00 is 7,168 in decimal. That cannot be anywhere near the end of a 16K micro so clearly 0x1C00 is not the value to use. In fact it is 0x1C00 * 2 = 0x3800 (which is 14,366 - much more sensible for a 16K micro). If Atmel had just given it as 0x3800 in the first place no one would be confused.

 

They use this 16 bit addressing in flash because all AVR opcodes are some multiple of 2 bytes. So a 16KB micro only has room for a maximum 8,192 AVR instructions. So they would describe this as an 8Kword micro. But it's all just plain confusing!!

JABBA_JOE wrote:
So it means that the interrupt is a passive thing? I was thinking that the interrupt was an active thing... the harware would send actively the signal to the processor telling it to stop and manage the interrupt!
This a RISC micro. At the end of the day it tries to be as simple as possible just using logic gates. There aren't things like "micro coding" and stuff in there. It is just state driven logic.

JABBA_JOE wrote:
According to this, is correct to say that the processor is "polling" the interrupt after every opcode? This polling consumes some clocks?

You want to take a look at some FPGA development using VHDL or Verilog. The "tricky concept" you need to get your brain around when designing such logic is that it's not procedural with step by step processes. Instead at each tick of the master "Clock" all the processes happen simultaneously. So, like I say, an AVR CPu is not micro-coded with multiple steps to achieve each granular function it offers the end user. Instead the state logic moves on one step for every tick of F_CPU. So if you fill the micro with 1 cycle NOP opcodes (say) then for every tick of the main clock (1MHz. 8MHz, 3.6864MHz or whatever) the whole opcode and any subsequent interrupt checking/vectoring all occurs simultaneously on the single tick of the clock. So that stuff is effectively all happening at the same time as the NOP or INC or ADD or whatever is also being processed.

 

In effect you are reading too much "intelligence" into this process. They are only transistors!

Last Edited: Fri. Nov 18, 2016 - 02:07 PM
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Great!! Amazing! Thanks! I'll keep studying! cool

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