I am working on a project that consists of daisy chaining about 50 boards together each containing an ATMEGA1284P. There are 8 lines in and 8 out. In is 2X power and ground, usart tx and rx, a power enable, and a general I/o. Out is 2x power and ground, usart, and 2 i/o pins. When the first one boots, it sets one IO line low that loads the next board in a certain state and then sets another high to enable the next board's regulator enable. This goes on to the next and so on.
I only am testing about 20 boards right now and half the time it works fine, but the other half it may only enable 12 or 4 or 7 or none or 17...you get the point...it is random. Making a change and reprogramming 20 boards is a nuisance so hopefully someone can explain what might be going on here. Can the usart semi power up the next device and cause it to enter a weird state? I have the brown out fuse set for 1.8v and I'm powering it with 3.3, should I use 2.3? Should I set the port d...usart....to an output state, set all low, power up next, then configure usart? Any ideas would be greatly appreciated. Also...if I force a reset via watchdog on the first board it's worse....maybe 25% of the time all boards load. I can visably see when a board loads. An LED is present from an io line. One more thing, there is about a 300ms total delay from when one board is up and the next starts. I added this in the code.